198a2d214f
It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Acked-by: Stafford Horne <shorne@gmail.com> Message-Id: <1550073577-4248-1-git-send-email-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/*
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* OpenRISC float helper routines
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exception.h"
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#include "fpu/softfloat.h"
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static int ieee_ex_to_openrisc(int fexcp)
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{
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int ret = 0;
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if (fexcp & float_flag_invalid) {
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ret |= FPCSR_IVF;
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}
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if (fexcp & float_flag_overflow) {
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ret |= FPCSR_OVF;
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}
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if (fexcp & float_flag_underflow) {
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ret |= FPCSR_UNF;
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}
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if (fexcp & float_flag_divbyzero) {
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ret |= FPCSR_DZF;
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}
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if (fexcp & float_flag_inexact) {
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ret |= FPCSR_IXF;
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}
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return ret;
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}
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void HELPER(update_fpcsr)(CPUOpenRISCState *env)
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{
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int tmp = get_float_exception_flags(&env->fp_status);
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if (tmp) {
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set_float_exception_flags(0, &env->fp_status);
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tmp = ieee_ex_to_openrisc(tmp);
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if (tmp) {
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env->fpcsr |= tmp;
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if (env->fpcsr & FPCSR_FPEE) {
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helper_exception(env, EXCP_FPE);
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}
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}
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}
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}
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uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
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{
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return int32_to_float64(val, &env->fp_status);
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}
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uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
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{
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return int32_to_float32(val, &env->fp_status);
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}
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uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
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{
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return float32_to_int64(val, &env->fp_status);
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}
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uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
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{
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return float32_to_int32(val, &env->fp_status);
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}
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#define FLOAT_CALC(name) \
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uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ return float64_ ## name(fdt0, fdt1, &env->fp_status); } \
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uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ return float32_ ## name(fdt0, fdt1, &env->fp_status); }
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FLOAT_CALC(add)
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FLOAT_CALC(sub)
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FLOAT_CALC(mul)
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FLOAT_CALC(div)
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FLOAT_CALC(rem)
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#undef FLOAT_CALC
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uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a,
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uint64_t b, uint64_t c)
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{
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/* Note that or1ksim doesn't use fused operation. */
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b = float64_mul(b, c, &env->fp_status);
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return float64_add(a, b, &env->fp_status);
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}
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uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a,
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uint32_t b, uint32_t c)
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{
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/* Note that or1ksim doesn't use fused operation. */
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b = float32_mul(b, c, &env->fp_status);
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return float32_add(a, b, &env->fp_status);
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}
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#define FLOAT_CMP(name, impl) \
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target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
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uint64_t fdt0, uint64_t fdt1) \
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{ return float64_ ## impl(fdt0, fdt1, &env->fp_status); } \
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target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
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uint32_t fdt0, uint32_t fdt1) \
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{ return float32_ ## impl(fdt0, fdt1, &env->fp_status); }
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FLOAT_CMP(le, le)
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FLOAT_CMP(lt, lt)
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FLOAT_CMP(eq, eq_quiet)
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#undef FLOAT_CMP
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