qemu-e2k/hw/riscv
Bin Meng 7cfbb17f02 hw/riscv: Support the official CLINT DT bindings
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08 09:59:42 +10:00
..
Kconfig hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine 2021-05-11 20:02:06 +10:00
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
meson.build riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
microchip_pfsoc.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: Fix OT IBEX reset vector 2021-05-11 20:02:07 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_e.c hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] 2021-05-11 20:01:10 +10:00
sifive_u.c hw/riscv: Support the official CLINT DT bindings 2021-06-08 09:59:42 +10:00
spike.c hw/riscv: Support the official CLINT DT bindings 2021-06-08 09:59:42 +10:00
virt.c hw/riscv: Support the official CLINT DT bindings 2021-06-08 09:59:42 +10:00