010746ae1d
This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Message-Id: <20230302133709.30373-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> |
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msi.h | ||
msix.h | ||
pci_bridge.h | ||
pci_bus.h | ||
pci_device.h | ||
pci_host.h | ||
pci_ids.h | ||
pci_regs.h | ||
pci.h | ||
pcie_aer.h | ||
pcie_doe.h | ||
pcie_host.h | ||
pcie_port.h | ||
pcie_regs.h | ||
pcie_sriov.h | ||
pcie.h | ||
shpc.h | ||
slotid_cap.h |