Max Filippov 7f4faa2185 tests/tcg/xtensa: update test_fp1 for DFPU ... DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2020-08-21 12:48:16 -07:00
..
crt.S
fpu.h	tests/tcg/xtensa: update test_fp0_arith for DFPU	2020-08-21 12:48:15 -07:00
linker.ld.S
macros.inc	tests/tcg/xtensa: fix test execution on ISS	2020-08-21 12:48:15 -07:00
Makefile.softmmu-target	tests/tcg: use EXTRA_CFLAGS everywhere	2019-09-10 09:38:33 +01:00
test_b.S
test_bi.S
test_boolean.S
test_break.S
test_bz.S
test_cache.S
test_clamps.S
test_exclusive.S	target/xtensa: implement exclusive access option	2019-05-15 10:31:52 -07:00
test_extui.S
test_flix.S	target/xtensa: fix break_dependency for repeated resources	2019-03-21 21:47:50 -07:00
test_fp0_arith.S	tests/tcg/xtensa: expand madd tests	2020-08-21 12:48:15 -07:00
test_fp0_conv.S	tests/tcg/xtensa: update test_fp0_conv for DFPU	2020-08-21 12:48:16 -07:00
test_fp1.S	tests/tcg/xtensa: update test_fp1 for DFPU	2020-08-21 12:48:16 -07:00
test_fp_cpenable.S	tests/tcg/xtensa: add FPU2000 coprocessor tests	2019-02-28 04:43:24 -08:00
test_interrupt.S
test_loop.S
test_lsc.S	tests/tcg/xtensa: add LSCI/LSCX group tests	2019-02-28 04:43:23 -08:00
test_mac16.S
test_max.S
test_min.S
test_mmu.S
test_mul16.S
test_mul32.S
test_nsa.S
test_phys_mem.S
test_quo.S
test_rem.S
test_rst0.S
test_s32c1i.S
test_sar.S
test_sext.S
test_shift.S
test_sr.S
test_timer.S
test_windowed.S
vectors.S