24be5ae3a0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2654 c046a42c-6fe2-441c-8c8c-71466251a162
689 lines
20 KiB
C
689 lines
20 KiB
C
/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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#define BIOS_FILENAME "ppc_rom.bin"
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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extern int loglevel;
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extern FILE *logfile;
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \
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} else { \
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printf("%s : " fmt, __func__ , ##args); \
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} \
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} while (0)
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_IOPORT) { \
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fprintf(logfile, "%s: " fmt, __func__ , ##args); \
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} \
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} while (0)
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#else
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#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 13, 13 };
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#define NE2000_NB_MAX 6
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
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//static PITState *pit;
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000
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/* Speaker port 0x61 */
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int speaker_data_on;
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int dummy_refresh_clock;
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static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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#if 0
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speaker_data_on = (val >> 1) & 1;
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pit_set_gate(pit, 2, val & 1);
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#endif
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}
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static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
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{
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#if 0
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int out;
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out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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dummy_refresh_clock ^= 1;
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return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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(dummy_refresh_clock << 4);
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#endif
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return 0;
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}
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/* PCI intack register */
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/* Read-only register (?) */
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static void _PPC_intack_write (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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}
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static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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if (addr == 0xBFFFFFF0)
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retval = pic_intack_read(isa_pic);
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// printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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return retval;
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}
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
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{
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return _PPC_intack_read(addr);
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}
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap16(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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}
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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return bswap32(_PPC_intack_read(addr));
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#else
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return _PPC_intack_read(addr);
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#endif
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}
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static CPUWriteMemoryFunc *PPC_intack_write[] = {
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&_PPC_intack_write,
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&_PPC_intack_write,
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&_PPC_intack_write,
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};
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static CPUReadMemoryFunc *PPC_intack_read[] = {
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&PPC_intack_readb,
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&PPC_intack_readw,
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&PPC_intack_readl,
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};
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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}
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static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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}
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static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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}
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap16(retval);
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#endif
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return retval;
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}
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
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#ifdef TARGET_WORDS_BIGENDIAN
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retval = bswap32(retval);
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#endif
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return retval;
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}
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static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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&PPC_XCSR_writeb,
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&PPC_XCSR_writew,
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&PPC_XCSR_writel,
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};
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static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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&PPC_XCSR_readb,
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&PPC_XCSR_readw,
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&PPC_XCSR_readl,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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m48t59_t *nvram;
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uint8_t state;
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uint8_t syscontrol;
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uint8_t fake_io[2];
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int contiguous_map;
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int endian;
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} sysctrl_t;
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enum {
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STATE_HARDFILE = 0x01,
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};
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
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sysctrl->fake_io[addr - 0x0398] = val;
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}
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static uint32_t PREP_io_read (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
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sysctrl->fake_io[addr - 0x0398]);
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return sysctrl->fake_io[addr - 0x0398];
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}
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) {
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// cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
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}
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/* Check LE mode */
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if (val & 0x02) {
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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}
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break;
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case 0x0800:
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802:
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803:
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/* Motorola base module status register : read-only */
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break;
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case 0x0808:
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/* Hardfile light register */
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if (val & 1)
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sysctrl->state |= STATE_HARDFILE;
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else
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sysctrl->state &= ~STATE_HARDFILE;
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
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case 0x0814:
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C:
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850:
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
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default:
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printf("ERROR: unaffected IO port write: %04lx => %02x\n",
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(long)addr, val);
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break;
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}
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}
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092:
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/* Special port 92 */
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retval = 0x00;
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break;
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case 0x0800:
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */
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break;
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case 0x0802:
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
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break;
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case 0x0803:
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */
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break;
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case 0x080C:
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810:
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
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break;
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case 0x0814:
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/* L2 invalidate: don't care */
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break;
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case 0x0818:
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C:
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol;
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break;
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case 0x0823:
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/* */
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retval = 0x03; /* no L2 cache */
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break;
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case 0x0850:
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/* I/O map type register */
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retval = sysctrl->contiguous_map;
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break;
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default:
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printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
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break;
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}
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PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
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return retval;
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}
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static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
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target_phys_addr_t addr)
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{
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if (sysctrl->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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return addr;
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}
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static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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cpu_outb(NULL, addr, value);
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}
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static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inb(NULL, addr);
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return ret;
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}
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static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap16(value);
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#endif
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
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cpu_outw(NULL, addr, value);
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}
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static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inw(NULL, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap16(ret);
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#endif
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PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
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return ret;
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}
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static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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sysctrl_t *sysctrl = opaque;
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addr = prep_IO_address(sysctrl, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
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cpu_outl(NULL, addr, value);
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}
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static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
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{
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sysctrl_t *sysctrl = opaque;
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uint32_t ret;
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addr = prep_IO_address(sysctrl, addr);
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ret = cpu_inl(NULL, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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ret = bswap32(ret);
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#endif
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PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
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return ret;
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}
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CPUWriteMemoryFunc *PPC_prep_io_write[] = {
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&PPC_prep_io_writeb,
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&PPC_prep_io_writew,
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&PPC_prep_io_writel,
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};
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CPUReadMemoryFunc *PPC_prep_io_read[] = {
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&PPC_prep_io_readb,
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&PPC_prep_io_readw,
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&PPC_prep_io_readl,
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};
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#define NVRAM_SIZE 0x2000
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename,
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int snapshot, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env;
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char buf[1024];
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m48t59_t *nvram;
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int PPC_io_memory;
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int linux_boot, i, nb_nics1, bios_size;
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unsigned long bios_offset;
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uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
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ppc_def_t *def;
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PCIBus *pci_bus;
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qemu_irq *i8259;
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sysctrl = qemu_mallocz(sizeof(sysctrl_t));
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if (sysctrl == NULL)
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return;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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env = cpu_init();
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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/* Default CPU is a 604 */
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if (cpu_model == NULL)
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cpu_model = "604";
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ppc_find_by_name(cpu_model, &def);
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if (def == NULL) {
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cpu_abort(env, "Unable to find PowerPC CPU definition\n");
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}
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cpu_ppc_register(env, def);
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* allocate and load BIOS */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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exit(1);
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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if (linux_boot) {
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kernel_base = KERNEL_LOAD_ADDR;
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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}
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isa_mem_base = 0xc0000000;
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i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
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pci_bus = pci_prep_init(i8259);
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// pci_bus = i440fx_init();
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/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
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PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
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PPC_prep_io_write, sysctrl);
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cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
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/* init basic PC hardware */
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pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size, 0, 0);
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// openpic = openpic_init(0x00000000, 0xF0000000, 1);
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// pit = pit_init(0x40, i8259[0]);
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rtc_init(0x70, i8259[8]);
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serial_init(0x3f8, i8259[4], serial_hds[0]);
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nb_nics1 = nb_nics;
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if (nb_nics1 > NE2000_NB_MAX)
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nb_nics1 = NE2000_NB_MAX;
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for(i = 0; i < nb_nics1; i++) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
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isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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for(i = 0; i < 2; i++) {
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isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
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bs_table[2 * i], bs_table[2 * i + 1]);
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}
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i8042_init(i8259[1], i8259[12], 0x60);
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DMA_init(1);
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// AUD_init();
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// SB16_init();
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fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
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/* Register speaker port */
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register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
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register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
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/* Register fake IO ports for PREP */
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register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
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register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
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/* System control ports */
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register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
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register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
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register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
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register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
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/* PCI intack location */
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PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
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PPC_intack_write, NULL);
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cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
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/* PowerPC control and status register group */
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#if 0
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PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
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cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
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#endif
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if (usb_enabled) {
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usb_ohci_init_pci(pci_bus, 3, -1);
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}
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nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
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if (nvram == NULL)
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return;
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sysctrl->nvram = nvram;
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/* Initialise NVRAM */
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PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
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kernel_base, kernel_size,
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kernel_cmdline,
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initrd_base, initrd_size,
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/* XXX: need an option to load a NVRAM image */
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0,
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graphic_width, graphic_height, graphic_depth);
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/* Special port to get debug messages from Open-Firmware */
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register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
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}
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QEMUMachine prep_machine = {
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"prep",
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"PowerPC PREP platform",
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ppc_prep_init,
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};
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