298 lines
7.6 KiB
C
298 lines
7.6 KiB
C
/*
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* QEMU 8253/8254 interval timer emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <getopt.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include <sys/mman.h>
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#include <fcntl.h>
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#include <signal.h>
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#include <time.h>
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#include <sys/time.h>
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#include <malloc.h>
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#include <termios.h>
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#include <sys/poll.h>
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#include <errno.h>
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#include <sys/wait.h>
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#include <netinet/in.h>
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#include "cpu.h"
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#include "vl.h"
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#define RW_STATE_LSB 0
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#define RW_STATE_MSB 1
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#define RW_STATE_WORD0 2
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#define RW_STATE_WORD1 3
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#define RW_STATE_LATCHED_WORD0 4
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#define RW_STATE_LATCHED_WORD1 5
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PITChannelState pit_channels[3];
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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case 0:
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case 1:
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case 4:
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case 5:
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counter = (s->count - d) & 0xffff;
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break;
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case 3:
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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break;
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default:
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counter = s->count - (d % s->count);
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break;
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}
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return counter;
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}
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/* get pit output bit */
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int pit_get_out(PITChannelState *s)
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{
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uint64_t d;
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int out;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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out = (d >= s->count);
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break;
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case 1:
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out = (d < s->count);
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break;
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case 2:
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if ((d % s->count) == 0 && d != 0)
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out = 1;
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else
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out = 0;
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break;
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case 3:
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out = (d % s->count) < ((s->count + 1) >> 1);
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break;
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case 4:
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case 5:
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out = (d == s->count);
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break;
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}
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return out;
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}
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/* get the number of 0 to 1 transitions we had since we call this
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function */
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/* XXX: maybe better to use ticks precision to avoid getting edges
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twice if checks are done at very small intervals */
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int pit_get_out_edges(PITChannelState *s)
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{
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uint64_t d1, d2;
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int64_t ticks;
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int ret, v;
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ticks = cpu_get_ticks();
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d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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d2 = muldiv64(ticks - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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s->count_last_edge_check_time = ticks;
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switch(s->mode) {
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default:
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case 0:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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else
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ret = 0;
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break;
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case 1:
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ret = 0;
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break;
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case 2:
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d1 /= s->count;
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d2 /= s->count;
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ret = d2 - d1;
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break;
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case 3:
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v = s->count - ((s->count + 1) >> 1);
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d1 = (d1 + v) / s->count;
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d2 = (d2 + v) / s->count;
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ret = d2 - d1;
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break;
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case 4:
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case 5:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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else
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ret = 0;
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break;
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}
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return ret;
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}
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/* val must be 0 or 1 */
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void pit_set_gate(PITChannelState *s, int val)
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{
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switch(s->mode) {
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default:
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case 0:
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case 4:
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/* XXX: just disable/enable counting */
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break;
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case 1:
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case 5:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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}
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break;
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case 2:
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case 3:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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}
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/* XXX: disable/enable counting */
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break;
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}
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s->gate = val;
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}
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static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count = val;
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if (s == &pit_channels[0] && val <= pit_min_timer_count) {
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fprintf(stderr,
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"\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
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PIT_FREQ / pit_min_timer_count);
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}
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}
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void pit_ioport_write(CPUState *env, uint32_t addr, uint32_t val)
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{
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int channel, access;
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PITChannelState *s;
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addr &= 3;
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if (addr == 3) {
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channel = val >> 6;
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if (channel == 3)
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return;
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s = &pit_channels[channel];
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access = (val >> 4) & 3;
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switch(access) {
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case 0:
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s->latched_count = pit_get_count(s);
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s->rw_state = RW_STATE_LATCHED_WORD0;
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break;
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default:
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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s->rw_state = access - 1 + RW_STATE_LSB;
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break;
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}
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} else {
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s = &pit_channels[addr];
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switch(s->rw_state) {
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case RW_STATE_LSB:
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pit_load_count(s, val);
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break;
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case RW_STATE_MSB:
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pit_load_count(s, val << 8);
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break;
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case RW_STATE_WORD0:
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case RW_STATE_WORD1:
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if (s->rw_state & 1) {
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pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
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} else {
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s->latched_count = val;
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}
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s->rw_state ^= 1;
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break;
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}
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}
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}
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uint32_t pit_ioport_read(CPUState *env, uint32_t addr)
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{
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int ret, count;
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PITChannelState *s;
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addr &= 3;
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s = &pit_channels[addr];
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switch(s->rw_state) {
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case RW_STATE_LSB:
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case RW_STATE_MSB:
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case RW_STATE_WORD0:
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case RW_STATE_WORD1:
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count = pit_get_count(s);
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if (s->rw_state & 1)
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ret = (count >> 8) & 0xff;
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else
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ret = count & 0xff;
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if (s->rw_state & 2)
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s->rw_state ^= 1;
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break;
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default:
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case RW_STATE_LATCHED_WORD0:
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case RW_STATE_LATCHED_WORD1:
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if (s->rw_state & 1)
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ret = s->latched_count >> 8;
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else
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ret = s->latched_count & 0xff;
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s->rw_state ^= 1;
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break;
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}
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return ret;
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}
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void pit_init(void)
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{
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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s = &pit_channels[i];
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s->mode = 3;
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s->gate = (i != 2);
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pit_load_count(s, 0);
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}
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register_ioport_write(0x40, 4, pit_ioport_write, 1);
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register_ioport_read(0x40, 3, pit_ioport_read, 1);
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}
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