qemu-e2k/hw/riscv
Jason A. Donenfeld 64c75db3c5 riscv: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: qemu-riscv@nongnu.org
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20221025004327.568476-6-Jason@zx2c4.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-27 11:34:31 +01:00
..
Kconfig hw/riscv: Enable TPM backends 2022-04-29 10:48:48 +10:00
boot.c riscv: re-randomize rng-seed on reboot 2022-10-27 11:34:31 +01:00
meson.build hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines 2021-07-20 15:32:49 +02:00
microchip_pfsoc.c hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals 2022-09-07 09:18:33 +02:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: opentitan: Expose the resetvec as a SoC property 2022-09-27 07:04:38 +10:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() 2022-09-07 09:18:33 +02:00
sifive_e.c hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) 2022-05-24 10:38:50 +10:00
sifive_u.c hw/riscv: set machine->fdt in sifive_u_machine_init() 2022-10-17 16:15:10 -03:00
spike.c hw/riscv: set machine->fdt in spike_board_init() 2022-10-17 16:15:10 -03:00
virt.c hw/riscv: virt: Enable booting S-mode firmware from pflash 2022-10-14 14:29:50 +10:00