qemu-e2k/target
Peter Maydell 1aa4512ecd target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing
The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72
and which we (arguably dubiously) also provide in '-cpu max' has a
2 bit field for the number of processors in the cluster. On real
hardware this must be sufficient because it can only be configured
with up to 4 CPUs in the cluster. However on QEMU if the board code
does not explicitly configure the code into clusters with the right
CPU count we default to "give the value assuming that all CPUs in
the system are in a single cluster", which might be too big to fit
in the field.

Instead of just overflowing this 2-bit field, saturate to 3 (meaning
"4 CPUs", so at least we don't overwrite other fields in the register.
It's unlikely that any guest code really cares about the value in
this field; at least, if it does it probably also wants the system
to be more closely matching real hardware, i.e. not to have more
than 4 CPUs.

This issue has been present since the L2CTLR was first added in
commit 377a44ec8f back in 2014. It was only noticed because
Coverity complains (CID 1509227) that the shift might overflow 32 bits
and inadvertently sign extend into the top half of the 64 bit value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512170223.3801643-2-peter.maydell@linaro.org
2023-05-18 11:39:33 +01:00
..
alpha
arm target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing 2023-05-18 11:39:33 +01:00
avr
cris
hexagon
hppa
i386 target/i386: Add EPYC-Genoa model to support Zen 4 processor series 2023-05-08 16:35:30 +02:00
loongarch target/loongarch: Do not include tcg-ldst.h 2023-05-11 09:53:41 +01:00
m68k target/m68k: Fix gen_load_fp for OS_LONG 2023-05-11 09:49:25 +01:00
microblaze
mips target/mips: Use MO_ALIGN instead of 0 2023-05-11 09:53:41 +01:00
nios2 target/nios2: Remove TARGET_ALIGNED_ONLY 2023-05-11 09:53:41 +01:00
openrisc target/openrisc: Setup FPU for detecting tininess before rounding 2023-05-11 15:40:28 +01:00
ppc
riscv
rx
s390x target/s390x: Fix EXECUTE of relative branches 2023-05-16 09:14:18 +02:00
sh4 target/sh4: Use MO_ALIGN where required 2023-05-11 09:53:41 +01:00
sparc
tricore
xtensa
Kconfig
meson.build