315 lines
8.9 KiB
C
315 lines
8.9 KiB
C
/*
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* QEMU MIPS Jazz support
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*
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* Copyright (c) 2007-2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "mips.h"
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#include "mips_cpudevs.h"
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#include "pc.h"
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#include "isa.h"
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#include "fdc.h"
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#include "sysemu.h"
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#include "arch_init.h"
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#include "boards.h"
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#include "net.h"
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#include "esp.h"
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#include "mips-bios.h"
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#include "loader.h"
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#include "mc146818rtc.h"
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#include "blockdev.h"
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enum jazz_model_e
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{
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JAZZ_MAGNUM,
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JAZZ_PICA61,
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};
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
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{
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return cpu_inw(0x71);
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}
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static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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cpu_outw(0x71, val & 0xff);
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}
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static CPUReadMemoryFunc * const rtc_read[3] = {
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rtc_readb,
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rtc_readb,
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rtc_readb,
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};
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static CPUWriteMemoryFunc * const rtc_write[3] = {
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rtc_writeb,
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rtc_writeb,
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rtc_writeb,
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};
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static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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/* Nothing to do. That is only to ensure that
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* the current DMA acknowledge cycle is completed. */
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}
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static CPUReadMemoryFunc * const dma_dummy_read[3] = {
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NULL,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
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dma_dummy_writeb,
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dma_dummy_writeb,
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dma_dummy_writeb,
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};
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#define MAGNUM_BIOS_SIZE_MAX 0x7e000
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#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
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static void cpu_request_exit(void *opaque, int irq, int level)
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{
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CPUState *env = cpu_single_env;
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if (env && level) {
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cpu_exit(env);
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}
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}
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static
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void mips_jazz_init (ram_addr_t ram_size,
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const char *cpu_model,
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enum jazz_model_e jazz_model)
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{
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char *filename;
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int bios_size, n;
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CPUState *env;
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qemu_irq *rc4030, *i8259;
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rc4030_dma *dmas;
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void* rc4030_opaque;
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int s_rtc, s_dma_dummy;
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NICInfo *nd;
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ISADevice *pit;
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DriveInfo *fds[MAX_FD];
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qemu_irq esp_reset, dma_enable;
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qemu_irq *cpu_exit_irq;
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ram_addr_t ram_offset;
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ram_addr_t bios_offset;
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/* init CPUs */
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if (cpu_model == NULL) {
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#ifdef TARGET_MIPS64
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cpu_model = "R4000";
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#else
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/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
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cpu_model = "24Kf";
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#endif
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
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cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
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bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
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cpu_register_physical_memory(0x1fc00000LL,
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
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cpu_register_physical_memory(0xfff00000LL,
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
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/* load the BIOS image. */
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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bios_size = load_image_targphys(filename, 0xfff00000LL,
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MAGNUM_BIOS_SIZE);
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qemu_free(filename);
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} else {
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bios_size = -1;
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}
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if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
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fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
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bios_name);
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exit(1);
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}
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/* Init CPU internal devices */
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cpu_mips_irq_init_cpu(env);
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cpu_mips_clock_init(env);
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/* Chipset */
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rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
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s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
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/* ISA devices */
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i8259 = i8259_init(env->irq[4]);
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isa_bus_new(NULL);
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isa_bus_irqs(i8259);
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cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
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DMA_init(0, cpu_exit_irq);
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pit = pit_init(0x40, 0);
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pcspk_init(pit);
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/* ISA IO space at 0x90000000 */
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isa_mmio_init(0x90000000, 0x01000000);
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isa_mem_base = 0x11000000;
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/* Video card */
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switch (jazz_model) {
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case JAZZ_MAGNUM:
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g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
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break;
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case JAZZ_PICA61:
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isa_vga_mm_init(0x40000000, 0x60000000, 0);
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break;
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default:
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break;
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}
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/* Network controller */
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for (n = 0; n < nb_nics; n++) {
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nd = &nd_table[n];
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if (!nd->model)
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nd->model = qemu_strdup("dp83932");
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if (strcmp(nd->model, "dp83932") == 0) {
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dp83932_init(nd, 0x80001000, 2, rc4030[4],
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rc4030_opaque, rc4030_dma_memory_rw);
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break;
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} else if (strcmp(nd->model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: dp83932\n");
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exit(1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
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exit(1);
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}
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}
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/* SCSI adapter */
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esp_init(0x80002000, 0,
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rc4030_dma_read, rc4030_dma_write, dmas[0],
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rc4030[5], &esp_reset, &dma_enable);
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/* Floppy */
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if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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fprintf(stderr, "qemu: too many floppy drives\n");
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exit(1);
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}
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for (n = 0; n < MAX_FD; n++) {
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fds[n] = drive_get(IF_FLOPPY, 0, n);
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}
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fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
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/* Real time clock */
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rtc_init(1980, NULL);
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s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
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DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
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/* Keyboard (i8042) */
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i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
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/* Serial ports */
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if (serial_hds[0]) {
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#ifdef TARGET_WORDS_BIGENDIAN
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serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
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#else
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serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
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#endif
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}
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if (serial_hds[1]) {
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#ifdef TARGET_WORDS_BIGENDIAN
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serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
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#else
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serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
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#endif
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}
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/* Parallel port */
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if (parallel_hds[0])
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parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
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/* Sound card */
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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audio_init(i8259, NULL);
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/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
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ds1225y_init(0x80009000, "nvram");
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/* LED indicator */
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jazz_led_init(0x8000f000);
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}
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static
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void mips_magnum_init (ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
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}
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static
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void mips_pica61_init (ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
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}
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static QEMUMachine mips_magnum_machine = {
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.name = "magnum",
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.desc = "MIPS Magnum",
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.init = mips_magnum_init,
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.use_scsi = 1,
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};
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static QEMUMachine mips_pica61_machine = {
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.name = "pica61",
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.desc = "Acer Pica 61",
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.init = mips_pica61_init,
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.use_scsi = 1,
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};
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static void mips_jazz_machine_init(void)
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{
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qemu_register_machine(&mips_magnum_machine);
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qemu_register_machine(&mips_pica61_machine);
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}
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machine_init(mips_jazz_machine_init);
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