6ef5843182
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
867 lines
24 KiB
C
867 lines
24 KiB
C
/*
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* RISC-V emulation for qemu: main translation routines.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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#include "disas/disas.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-gen.h"
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#include "exec/translator.h"
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#include "exec/log.h"
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#include "instmap.h"
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/* global register indices */
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static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
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static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
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static TCGv load_res;
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static TCGv load_val;
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#include "exec/gen-icount.h"
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typedef struct DisasContext {
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DisasContextBase base;
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/* pc_succ_insn points to the instruction following base.pc_next */
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target_ulong pc_succ_insn;
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target_ulong priv_ver;
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bool virt_enabled;
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uint32_t opcode;
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uint32_t mstatus_fs;
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uint32_t misa;
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uint32_t mem_idx;
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/* Remember the rounding mode encoded in the previous fp instruction,
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which we have already installed into env->fp_status. Or -1 for
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no previous fp instruction. Note that we exit the TB when writing
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to any system register, which includes CSR_FRM, so we do not have
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to reset this known value. */
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int frm;
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bool ext_ifencei;
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bool hlsx;
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/* vector extension */
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bool vill;
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uint8_t lmul;
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uint8_t sew;
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uint16_t vlen;
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uint16_t mlen;
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bool vl_eq_vlmax;
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CPUState *cs;
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} DisasContext;
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static inline bool has_ext(DisasContext *ctx, uint32_t ext)
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{
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return ctx->misa & ext;
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}
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#ifdef TARGET_RISCV32
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# define is_32bit(ctx) true
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#elif defined(CONFIG_USER_ONLY)
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# define is_32bit(ctx) false
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#else
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static inline bool is_32bit(DisasContext *ctx)
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{
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return (ctx->misa & RV32) == RV32;
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}
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#endif
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/*
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* RISC-V requires NaN-boxing of narrower width floating point values.
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* This applies when a 32-bit value is assigned to a 64-bit FP register.
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* For consistency and simplicity, we nanbox results even when the RVD
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* extension is not present.
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*/
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static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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{
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tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
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}
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/*
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* A narrow n-bit operation, where n < FLEN, checks that input operands
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* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
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* If so, the least-significant bits of the input are used, otherwise the
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* input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
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*
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* Here, the result is always nan-boxed, even the canonical nan.
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*/
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static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
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{
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TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
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TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull);
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tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
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tcg_temp_free_i64(t_max);
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tcg_temp_free_i64(t_nan);
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}
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static void generate_exception(DisasContext *ctx, int excp)
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{
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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TCGv_i32 helper_tmp = tcg_const_i32(excp);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void generate_exception_mtval(DisasContext *ctx, int excp)
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{
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
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TCGv_i32 helper_tmp = tcg_const_i32(excp);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_debug(void)
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{
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TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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}
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/* Wrapper around tcg_gen_exit_tb that handles single stepping */
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static void exit_tb(DisasContext *ctx)
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{
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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}
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/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
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static void lookup_and_goto_ptr(DisasContext *ctx)
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{
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if (ctx->base.singlestep_enabled) {
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gen_exception_debug();
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} else {
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tcg_gen_lookup_and_goto_ptr();
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}
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}
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static void gen_exception_illegal(DisasContext *ctx)
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{
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generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
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}
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static void gen_exception_inst_addr_mis(DisasContext *ctx)
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{
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generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
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}
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static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
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{
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if (unlikely(ctx->base.singlestep_enabled)) {
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return false;
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}
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#ifndef CONFIG_USER_ONLY
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return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
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#else
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return true;
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#endif
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}
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static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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if (use_goto_tb(ctx, dest)) {
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/* chaining is only allowed when the jump is to the same page */
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_pc, dest);
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/* No need to check for single stepping here as use_goto_tb() will
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* return false in case of single stepping.
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*/
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tcg_gen_exit_tb(ctx->base.tb, n);
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} else {
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tcg_gen_movi_tl(cpu_pc, dest);
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lookup_and_goto_ptr(ctx);
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}
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}
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/* Wrapper for getting reg values - need to check of reg is zero since
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* cpu_gpr[0] is not actually allocated
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*/
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static inline void gen_get_gpr(TCGv t, int reg_num)
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{
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if (reg_num == 0) {
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tcg_gen_movi_tl(t, 0);
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} else {
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tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
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}
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}
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/* Wrapper for setting reg values - need to check of reg is zero since
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* cpu_gpr[0] is not actually allocated. this is more for safety purposes,
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* since we usually avoid calling the OP_TYPE_gen function if we see a write to
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* $zero
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*/
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static inline void gen_set_gpr(int reg_num_dst, TCGv t)
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{
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if (reg_num_dst != 0) {
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tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
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}
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}
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static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv rl = tcg_temp_new();
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TCGv rh = tcg_temp_new();
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tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
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/* fix up for one negative */
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tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
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tcg_gen_and_tl(rl, rl, arg2);
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tcg_gen_sub_tl(ret, rh, rl);
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tcg_temp_free(rl);
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tcg_temp_free(rh);
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}
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static void gen_div(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, cond2, zeroreg, resultopt1;
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/*
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* Handle by altering args to tcg_gen_div to produce req'd results:
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* For overflow: want source1 in source1 and 1 in source2
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* For div by zero: want -1 in source1 and 1 in source2 -> -1 result
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*/
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cond1 = tcg_temp_new();
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cond2 = tcg_temp_new();
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zeroreg = tcg_const_tl(0);
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resultopt1 = tcg_temp_new();
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tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
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((target_ulong)1) << (TARGET_LONG_BITS - 1));
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tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
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/* if div by zero, set source1 to -1, otherwise don't change */
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tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
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resultopt1);
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/* if overflow or div by zero, set source2 to 1, else don't change */
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tcg_gen_or_tl(cond1, cond1, cond2);
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tcg_gen_movi_tl(resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_div_tl(ret, source1, source2);
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tcg_temp_free(cond1);
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tcg_temp_free(cond2);
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tcg_temp_free(zeroreg);
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tcg_temp_free(resultopt1);
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}
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static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, zeroreg, resultopt1;
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cond1 = tcg_temp_new();
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zeroreg = tcg_const_tl(0);
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resultopt1 = tcg_temp_new();
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
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tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
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tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
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resultopt1);
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tcg_gen_movi_tl(resultopt1, (target_ulong)1);
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tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_divu_tl(ret, source1, source2);
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tcg_temp_free(cond1);
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tcg_temp_free(zeroreg);
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tcg_temp_free(resultopt1);
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}
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static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, cond2, zeroreg, resultopt1;
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cond1 = tcg_temp_new();
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cond2 = tcg_temp_new();
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zeroreg = tcg_const_tl(0);
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resultopt1 = tcg_temp_new();
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tcg_gen_movi_tl(resultopt1, 1L);
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
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(target_ulong)1 << (TARGET_LONG_BITS - 1));
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tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
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/* if overflow or div by zero, set source2 to 1, else don't change */
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tcg_gen_or_tl(cond2, cond1, cond2);
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tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
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resultopt1);
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tcg_gen_rem_tl(resultopt1, source1, source2);
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/* if div by zero, just return the original dividend */
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tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
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source1);
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tcg_temp_free(cond1);
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tcg_temp_free(cond2);
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tcg_temp_free(zeroreg);
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tcg_temp_free(resultopt1);
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}
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static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
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{
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TCGv cond1, zeroreg, resultopt1;
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cond1 = tcg_temp_new();
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zeroreg = tcg_const_tl(0);
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resultopt1 = tcg_temp_new();
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tcg_gen_movi_tl(resultopt1, (target_ulong)1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
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tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
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resultopt1);
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tcg_gen_remu_tl(resultopt1, source1, source2);
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/* if div by zero, just return the original dividend */
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tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
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source1);
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tcg_temp_free(cond1);
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tcg_temp_free(zeroreg);
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tcg_temp_free(resultopt1);
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}
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static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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{
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target_ulong next_pc;
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/* check misaligned: */
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next_pc = ctx->base.pc_next + imm;
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if (!has_ext(ctx, RVC)) {
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if ((next_pc & 0x3) != 0) {
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gen_exception_inst_addr_mis(ctx);
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return;
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}
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}
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if (rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
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}
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gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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#ifndef CONFIG_USER_ONLY
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/* The states of mstatus_fs are:
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* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
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* We will have already diagnosed disabled state,
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* and need to turn initial/clean into dirty.
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*/
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static void mark_fs_dirty(DisasContext *ctx)
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{
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TCGv tmp;
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target_ulong sd;
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if (ctx->mstatus_fs == MSTATUS_FS) {
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return;
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}
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/* Remember the state change for the rest of the TB. */
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ctx->mstatus_fs = MSTATUS_FS;
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tmp = tcg_temp_new();
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sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
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if (ctx->virt_enabled) {
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tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
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tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
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}
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tcg_temp_free(tmp);
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}
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#else
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static inline void mark_fs_dirty(DisasContext *ctx) { }
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#endif
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static void gen_set_rm(DisasContext *ctx, int rm)
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{
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TCGv_i32 t0;
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if (ctx->frm == rm) {
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return;
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}
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ctx->frm = rm;
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t0 = tcg_const_i32(rm);
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gen_helper_set_rounding_mode(cpu_env, t0);
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tcg_temp_free_i32(t0);
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}
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static int ex_plus_1(DisasContext *ctx, int nf)
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{
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return nf + 1;
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}
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#define EX_SH(amount) \
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static int ex_shift_##amount(DisasContext *ctx, int imm) \
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{ \
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return imm << amount; \
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}
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EX_SH(1)
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EX_SH(2)
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EX_SH(3)
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EX_SH(4)
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EX_SH(12)
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#define REQUIRE_EXT(ctx, ext) do { \
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if (!has_ext(ctx, ext)) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_64BIT(ctx) do { \
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if (is_32bit(ctx)) { \
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return false; \
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} \
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} while (0)
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static int ex_rvc_register(DisasContext *ctx, int reg)
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{
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return 8 + reg;
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}
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static int ex_rvc_shifti(DisasContext *ctx, int imm)
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{
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/* For RV128 a shamt of 0 means a shift by 64. */
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return imm ? imm : 64;
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}
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/* Include the auto-generated decoder for 32 bit insn */
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#include "decode-insn32.c.inc"
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static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
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void (*func)(TCGv, TCGv, target_long))
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{
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TCGv source1;
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source1 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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(*func)(source1, source1, a->imm);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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return true;
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}
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static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
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void (*func)(TCGv, TCGv, TCGv))
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{
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TCGv source1, source2;
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source1 = tcg_temp_new();
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source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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tcg_gen_movi_tl(source2, a->imm);
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(*func)(source1, source1, source2);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_add_tl(ret, arg1, arg2);
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tcg_gen_ext32s_tl(ret, ret);
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}
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static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_sub_tl(ret, arg1, arg2);
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tcg_gen_ext32s_tl(ret, ret);
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}
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static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_mul_tl(ret, arg1, arg2);
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tcg_gen_ext32s_tl(ret, ret);
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}
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static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
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void(*func)(TCGv, TCGv, TCGv))
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{
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TCGv source1, source2;
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source1 = tcg_temp_new();
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source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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tcg_gen_ext32s_tl(source1, source1);
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tcg_gen_ext32s_tl(source2, source2);
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(*func)(source1, source1, source2);
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tcg_gen_ext32s_tl(source1, source1);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
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void(*func)(TCGv, TCGv, TCGv))
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{
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TCGv source1, source2;
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source1 = tcg_temp_new();
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source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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tcg_gen_ext32u_tl(source1, source1);
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tcg_gen_ext32u_tl(source2, source2);
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(*func)(source1, source1, source2);
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tcg_gen_ext32s_tl(source1, source1);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_deposit_tl(ret, arg1, arg2,
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TARGET_LONG_BITS / 2,
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TARGET_LONG_BITS / 2);
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}
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static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
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tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
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tcg_temp_free(t);
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}
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static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext8u_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
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tcg_temp_free(t);
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}
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static void gen_ctzw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
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tcg_gen_ctzi_tl(ret, ret, 64);
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}
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static void gen_clzw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ext32u_tl(ret, arg1);
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tcg_gen_clzi_tl(ret, ret, 64);
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tcg_gen_subi_tl(ret, ret, 32);
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}
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static void gen_cpopw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ext32u_tl(arg1, arg1);
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tcg_gen_ctpop_tl(ret, arg1);
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}
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static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext16s_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
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tcg_temp_free(t);
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}
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static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, 16);
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tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
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tcg_gen_ext32s_tl(ret, ret);
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tcg_temp_free(t);
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}
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static bool gen_arith(DisasContext *ctx, arg_r *a,
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void(*func)(TCGv, TCGv, TCGv))
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{
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TCGv source1, source2;
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source1 = tcg_temp_new();
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source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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(*func)(source1, source1, source2);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static bool gen_shift(DisasContext *ctx, arg_r *a,
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void(*func)(TCGv, TCGv, TCGv))
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{
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TCGv source1 = tcg_temp_new();
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TCGv source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
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(*func)(source1, source1, source2);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUState *cpu = ctx->cs;
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CPURISCVState *env = cpu->env_ptr;
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return cpu_ldl_code(env, pc);
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}
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static void gen_ctz(TCGv ret, TCGv arg1)
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{
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tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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static void gen_clz(TCGv ret, TCGv arg1)
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{
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tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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static bool gen_unary(DisasContext *ctx, arg_r2 *a,
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void(*func)(TCGv, TCGv))
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{
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TCGv source = tcg_temp_new();
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gen_get_gpr(source, a->rs1);
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(*func)(source, source);
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gen_set_gpr(a->rd, source);
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tcg_temp_free(source);
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return true;
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}
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/* Include insn module translation function */
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#include "insn_trans/trans_rvi.c.inc"
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#include "insn_trans/trans_rvm.c.inc"
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#include "insn_trans/trans_rva.c.inc"
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#include "insn_trans/trans_rvf.c.inc"
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#include "insn_trans/trans_rvd.c.inc"
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#include "insn_trans/trans_rvh.c.inc"
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#include "insn_trans/trans_rvv.c.inc"
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#include "insn_trans/trans_rvb.c.inc"
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#include "insn_trans/trans_privileged.c.inc"
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/* Include the auto-generated decoder for 16 bit insn */
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#include "decode-insn16.c.inc"
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static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
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{
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/* check for compressed insn */
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if (extract16(opcode, 0, 2) != 3) {
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if (!has_ext(ctx, RVC)) {
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gen_exception_illegal(ctx);
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} else {
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ctx->pc_succ_insn = ctx->base.pc_next + 2;
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if (!decode_insn16(ctx, opcode)) {
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gen_exception_illegal(ctx);
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}
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}
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} else {
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uint32_t opcode32 = opcode;
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opcode32 = deposit32(opcode32, 16, 16,
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translator_lduw(env, ctx->base.pc_next + 2));
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ctx->pc_succ_insn = ctx->base.pc_next + 4;
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if (!decode_insn32(ctx, opcode32)) {
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gen_exception_illegal(ctx);
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}
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}
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}
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static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cs->env_ptr;
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RISCVCPU *cpu = RISCV_CPU(cs);
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uint32_t tb_flags = ctx->base.tb->flags;
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ctx->pc_succ_insn = ctx->base.pc_first;
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ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
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ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
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ctx->priv_ver = env->priv_ver;
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#if !defined(CONFIG_USER_ONLY)
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if (riscv_has_ext(env, RVH)) {
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ctx->virt_enabled = riscv_cpu_virt_enabled(env);
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} else {
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ctx->virt_enabled = false;
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}
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#else
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ctx->virt_enabled = false;
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#endif
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ctx->misa = env->misa;
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ctx->frm = -1; /* unknown rounding mode */
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ctx->ext_ifencei = cpu->cfg.ext_ifencei;
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ctx->vlen = cpu->cfg.vlen;
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ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
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ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
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ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
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ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
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ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
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ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
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ctx->cs = cs;
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}
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static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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{
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}
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static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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tcg_gen_insn_start(ctx->base.pc_next);
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}
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static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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const CPUBreakpoint *bp)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_exception_debug();
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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ctx->base.pc_next += 4;
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return true;
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}
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static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cpu->env_ptr;
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uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
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decode_opc(env, ctx, opcode16);
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ctx->base.pc_next = ctx->pc_succ_insn;
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if (ctx->base.is_jmp == DISAS_NEXT) {
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target_ulong page_start;
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page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
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if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
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ctx->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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}
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static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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switch (ctx->base.is_jmp) {
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case DISAS_TOO_MANY:
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gen_goto_tb(ctx, 0, ctx->base.pc_next);
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break;
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case DISAS_NORETURN:
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
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{
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#ifndef CONFIG_USER_ONLY
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RISCVCPU *rvcpu = RISCV_CPU(cpu);
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CPURISCVState *env = &rvcpu->env;
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#endif
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qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
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#ifndef CONFIG_USER_ONLY
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qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
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#endif
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log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
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}
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static const TranslatorOps riscv_tr_ops = {
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.init_disas_context = riscv_tr_init_disas_context,
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.tb_start = riscv_tr_tb_start,
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.insn_start = riscv_tr_insn_start,
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.breakpoint_check = riscv_tr_breakpoint_check,
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.translate_insn = riscv_tr_translate_insn,
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.tb_stop = riscv_tr_tb_stop,
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.disas_log = riscv_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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{
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DisasContext ctx;
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translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
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}
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void riscv_translate_init(void)
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{
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int i;
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/* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
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/* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
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/* registers, unless you specifically block reads/writes to reg 0 */
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cpu_gpr[0] = NULL;
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for (i = 1; i < 32; i++) {
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cpu_gpr[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
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}
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for (i = 0; i < 32; i++) {
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cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
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offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
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}
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cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
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cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
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load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
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"load_res");
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load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
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"load_val");
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}
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