5371f5cd71
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
notice:
The fpu xml from gdb 8.3 has unused register #, 65 and make first
csr register # become 69. We register extra register on gdb to correct
csr offset calculation
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
397 lines
9.3 KiB
C
397 lines
9.3 KiB
C
/*
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* RISC-V GDB Server Stub
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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#include "cpu.h"
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/*
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* The GDB CSR xml files list them in documentation order, not numerical order,
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* and are missing entries for unnamed CSRs. So we need to map the gdb numbers
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* to the hardware numbers.
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*/
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static int csr_register_map[] = {
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CSR_USTATUS,
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CSR_UIE,
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CSR_UTVEC,
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CSR_USCRATCH,
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CSR_UEPC,
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CSR_UCAUSE,
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CSR_UTVAL,
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CSR_UIP,
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CSR_FFLAGS,
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CSR_FRM,
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CSR_FCSR,
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CSR_CYCLE,
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CSR_TIME,
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CSR_INSTRET,
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CSR_HPMCOUNTER3,
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CSR_HPMCOUNTER4,
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CSR_HPMCOUNTER5,
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CSR_HPMCOUNTER6,
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CSR_HPMCOUNTER7,
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CSR_HPMCOUNTER8,
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CSR_HPMCOUNTER9,
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CSR_HPMCOUNTER10,
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CSR_HPMCOUNTER11,
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CSR_HPMCOUNTER12,
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CSR_HPMCOUNTER13,
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CSR_HPMCOUNTER14,
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CSR_HPMCOUNTER15,
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CSR_HPMCOUNTER16,
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CSR_HPMCOUNTER17,
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CSR_HPMCOUNTER18,
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CSR_HPMCOUNTER19,
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CSR_HPMCOUNTER20,
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CSR_HPMCOUNTER21,
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CSR_HPMCOUNTER22,
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CSR_HPMCOUNTER23,
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CSR_HPMCOUNTER24,
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CSR_HPMCOUNTER25,
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CSR_HPMCOUNTER26,
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CSR_HPMCOUNTER27,
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CSR_HPMCOUNTER28,
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CSR_HPMCOUNTER29,
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CSR_HPMCOUNTER30,
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CSR_HPMCOUNTER31,
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CSR_CYCLEH,
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CSR_TIMEH,
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CSR_INSTRETH,
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CSR_HPMCOUNTER3H,
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CSR_HPMCOUNTER4H,
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CSR_HPMCOUNTER5H,
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CSR_HPMCOUNTER6H,
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CSR_HPMCOUNTER7H,
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CSR_HPMCOUNTER8H,
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CSR_HPMCOUNTER9H,
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CSR_HPMCOUNTER10H,
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CSR_HPMCOUNTER11H,
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CSR_HPMCOUNTER12H,
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CSR_HPMCOUNTER13H,
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CSR_HPMCOUNTER14H,
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CSR_HPMCOUNTER15H,
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CSR_HPMCOUNTER16H,
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CSR_HPMCOUNTER17H,
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CSR_HPMCOUNTER18H,
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CSR_HPMCOUNTER19H,
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CSR_HPMCOUNTER20H,
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CSR_HPMCOUNTER21H,
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CSR_HPMCOUNTER22H,
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CSR_HPMCOUNTER23H,
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CSR_HPMCOUNTER24H,
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CSR_HPMCOUNTER25H,
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CSR_HPMCOUNTER26H,
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CSR_HPMCOUNTER27H,
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CSR_HPMCOUNTER28H,
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CSR_HPMCOUNTER29H,
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CSR_HPMCOUNTER30H,
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CSR_HPMCOUNTER31H,
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CSR_SSTATUS,
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CSR_SEDELEG,
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CSR_SIDELEG,
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CSR_SIE,
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CSR_STVEC,
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CSR_SCOUNTEREN,
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CSR_SSCRATCH,
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CSR_SEPC,
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CSR_SCAUSE,
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CSR_STVAL,
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CSR_SIP,
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CSR_SATP,
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CSR_MVENDORID,
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CSR_MARCHID,
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CSR_MIMPID,
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CSR_MHARTID,
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CSR_MSTATUS,
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CSR_MISA,
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CSR_MEDELEG,
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CSR_MIDELEG,
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CSR_MIE,
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CSR_MTVEC,
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CSR_MCOUNTEREN,
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CSR_MSCRATCH,
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CSR_MEPC,
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CSR_MCAUSE,
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CSR_MTVAL,
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CSR_MIP,
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CSR_PMPCFG0,
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CSR_PMPCFG1,
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CSR_PMPCFG2,
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CSR_PMPCFG3,
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CSR_PMPADDR0,
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CSR_PMPADDR1,
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CSR_PMPADDR2,
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CSR_PMPADDR3,
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CSR_PMPADDR4,
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CSR_PMPADDR5,
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CSR_PMPADDR6,
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CSR_PMPADDR7,
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CSR_PMPADDR8,
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CSR_PMPADDR9,
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CSR_PMPADDR10,
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CSR_PMPADDR11,
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CSR_PMPADDR12,
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CSR_PMPADDR13,
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CSR_PMPADDR14,
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CSR_PMPADDR15,
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CSR_MCYCLE,
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CSR_MINSTRET,
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CSR_MHPMCOUNTER3,
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CSR_MHPMCOUNTER4,
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CSR_MHPMCOUNTER5,
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CSR_MHPMCOUNTER6,
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CSR_MHPMCOUNTER7,
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CSR_MHPMCOUNTER8,
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CSR_MHPMCOUNTER9,
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CSR_MHPMCOUNTER10,
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CSR_MHPMCOUNTER11,
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CSR_MHPMCOUNTER12,
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CSR_MHPMCOUNTER13,
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CSR_MHPMCOUNTER14,
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CSR_MHPMCOUNTER15,
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CSR_MHPMCOUNTER16,
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CSR_MHPMCOUNTER17,
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CSR_MHPMCOUNTER18,
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CSR_MHPMCOUNTER19,
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CSR_MHPMCOUNTER20,
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CSR_MHPMCOUNTER21,
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CSR_MHPMCOUNTER22,
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CSR_MHPMCOUNTER23,
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CSR_MHPMCOUNTER24,
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CSR_MHPMCOUNTER25,
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CSR_MHPMCOUNTER26,
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CSR_MHPMCOUNTER27,
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CSR_MHPMCOUNTER28,
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CSR_MHPMCOUNTER29,
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CSR_MHPMCOUNTER30,
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CSR_MHPMCOUNTER31,
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CSR_MCYCLEH,
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CSR_MINSTRETH,
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CSR_MHPMCOUNTER3H,
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CSR_MHPMCOUNTER4H,
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CSR_MHPMCOUNTER5H,
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CSR_MHPMCOUNTER6H,
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CSR_MHPMCOUNTER7H,
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CSR_MHPMCOUNTER8H,
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CSR_MHPMCOUNTER9H,
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CSR_MHPMCOUNTER10H,
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CSR_MHPMCOUNTER11H,
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CSR_MHPMCOUNTER12H,
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CSR_MHPMCOUNTER13H,
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CSR_MHPMCOUNTER14H,
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CSR_MHPMCOUNTER15H,
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CSR_MHPMCOUNTER16H,
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CSR_MHPMCOUNTER17H,
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CSR_MHPMCOUNTER18H,
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CSR_MHPMCOUNTER19H,
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CSR_MHPMCOUNTER20H,
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CSR_MHPMCOUNTER21H,
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CSR_MHPMCOUNTER22H,
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CSR_MHPMCOUNTER23H,
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CSR_MHPMCOUNTER24H,
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CSR_MHPMCOUNTER25H,
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CSR_MHPMCOUNTER26H,
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CSR_MHPMCOUNTER27H,
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CSR_MHPMCOUNTER28H,
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CSR_MHPMCOUNTER29H,
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CSR_MHPMCOUNTER30H,
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CSR_MHPMCOUNTER31H,
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CSR_MHPMEVENT3,
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CSR_MHPMEVENT4,
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CSR_MHPMEVENT5,
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CSR_MHPMEVENT6,
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CSR_MHPMEVENT7,
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CSR_MHPMEVENT8,
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CSR_MHPMEVENT9,
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CSR_MHPMEVENT10,
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CSR_MHPMEVENT11,
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CSR_MHPMEVENT12,
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CSR_MHPMEVENT13,
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CSR_MHPMEVENT14,
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CSR_MHPMEVENT15,
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CSR_MHPMEVENT16,
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CSR_MHPMEVENT17,
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CSR_MHPMEVENT18,
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CSR_MHPMEVENT19,
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CSR_MHPMEVENT20,
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CSR_MHPMEVENT21,
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CSR_MHPMEVENT22,
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CSR_MHPMEVENT23,
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CSR_MHPMEVENT24,
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CSR_MHPMEVENT25,
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CSR_MHPMEVENT26,
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CSR_MHPMEVENT27,
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CSR_MHPMEVENT28,
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CSR_MHPMEVENT29,
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CSR_MHPMEVENT30,
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CSR_MHPMEVENT31,
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CSR_TSELECT,
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CSR_TDATA1,
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CSR_TDATA2,
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CSR_TDATA3,
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CSR_DCSR,
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CSR_DPC,
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CSR_DSCRATCH,
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CSR_HSTATUS,
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CSR_HEDELEG,
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CSR_HIDELEG,
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CSR_HIE,
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CSR_HTVEC,
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CSR_HSCRATCH,
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CSR_HEPC,
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CSR_HCAUSE,
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CSR_HBADADDR,
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CSR_HIP,
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CSR_MBASE,
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CSR_MBOUND,
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CSR_MIBASE,
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CSR_MIBOUND,
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CSR_MDBASE,
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CSR_MDBOUND,
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CSR_MUCOUNTEREN,
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CSR_MSCOUNTEREN,
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CSR_MHCOUNTEREN,
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};
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int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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}
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return 0;
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}
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int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n == 0) {
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/* discard writes to x0 */
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return sizeof(target_ulong);
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} else if (n < 32) {
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env->gpr[n] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n == 32) {
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env->pc = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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return gdb_get_reg64(mem_buf, env->fpr[n]);
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = 0;
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int result;
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/*
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* CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
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if (result == 0) {
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return gdb_get_regl(mem_buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
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return sizeof(uint64_t);
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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/*
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* CSR_FFLAGS is at index 8 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
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if (result == 0) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < ARRAY_SIZE(csr_register_map)) {
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target_ulong val = 0;
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int result;
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result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
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if (result == 0) {
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return gdb_get_regl(mem_buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < ARRAY_SIZE(csr_register_map)) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
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if (result == 0) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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#if defined(TARGET_RISCV32)
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if (env->misa & RVF) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-32bit-fpu.xml", 0);
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}
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gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
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4096, "riscv-32bit-csr.xml", 0);
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#elif defined(TARGET_RISCV64)
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if (env->misa & RVF) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-64bit-fpu.xml", 0);
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}
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gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
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4096, "riscv-64bit-csr.xml", 0);
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#endif
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}
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