355 lines
13 KiB
C
355 lines
13 KiB
C
/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to dea
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* split out from pci.c
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*/
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#include "pci_bridge.h"
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#include "pci_internals.h"
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#include "range.h"
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/* PCI bridge subsystem vendor ID helper functions */
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#define PCI_SSVID_SIZEOF 8
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#define PCI_SSVID_SVID 4
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#define PCI_SSVID_SSID 6
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int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
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uint16_t svid, uint16_t ssid)
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{
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int pos;
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pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
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if (pos < 0) {
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return pos;
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}
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pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
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pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
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return pos;
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}
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/* Accessor function to get parent bridge device from pci bus. */
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PCIDevice *pci_bridge_get_device(PCIBus *bus)
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{
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return bus->parent_dev;
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}
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/* Accessor function to get secondary bus from pci-to-pci bridge device */
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PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
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{
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return &br->sec_bus;
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}
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static uint32_t pci_config_get_io_base(const PCIDevice *d,
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uint32_t base, uint32_t base_upper16)
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{
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uint32_t val;
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val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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}
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return val;
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}
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static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
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{
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return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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<< 16;
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}
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static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
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uint32_t base, uint32_t upper)
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{
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pcibus_t tmp;
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pcibus_t val;
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tmp = (pcibus_t)pci_get_word(d->config + base);
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val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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if (tmp & PCI_PREF_RANGE_TYPE_64) {
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val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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}
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return val;
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}
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/* accessor function to get bridge filtering base address */
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pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
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{
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pcibus_t base;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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base = pci_config_get_io_base(bridge,
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PCI_IO_BASE, PCI_IO_BASE_UPPER16);
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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base = pci_config_get_pref_base(
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bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
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} else {
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base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
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}
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}
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return base;
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}
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/* accessor funciton to get bridge filtering limit */
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pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
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{
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pcibus_t limit;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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limit = pci_config_get_io_base(bridge,
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PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
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limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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limit = pci_config_get_pref_base(
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bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
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} else {
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limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
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}
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limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
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}
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return limit;
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}
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static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
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uint8_t type, const char *name,
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MemoryRegion *space,
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MemoryRegion *parent_space,
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bool enabled)
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{
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pcibus_t base = pci_bridge_get_base(&bridge->dev, type);
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pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type);
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/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
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* Apparently no way to do this with existing memory APIs. */
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pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
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memory_region_init_alias(alias, name, space, base, size);
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memory_region_add_subregion_overlap(parent_space, base, alias, 1);
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}
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static void pci_bridge_cleanup_alias(MemoryRegion *alias,
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MemoryRegion *parent_space)
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{
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memory_region_del_subregion(parent_space, alias);
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memory_region_destroy(alias);
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}
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static void pci_bridge_region_init(PCIBridge *br)
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{
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PCIBus *parent = br->dev.bus;
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uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND);
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pci_bridge_init_alias(br, &br->alias_pref_mem,
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PCI_BASE_ADDRESS_MEM_PREFETCH,
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"pci_bridge_pref_mem",
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&br->address_space_mem,
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parent->address_space_mem,
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cmd & PCI_COMMAND_MEMORY);
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pci_bridge_init_alias(br, &br->alias_mem,
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PCI_BASE_ADDRESS_SPACE_MEMORY,
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"pci_bridge_mem",
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&br->address_space_mem,
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parent->address_space_mem,
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cmd & PCI_COMMAND_MEMORY);
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pci_bridge_init_alias(br, &br->alias_io,
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PCI_BASE_ADDRESS_SPACE_IO,
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"pci_bridge_io",
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&br->address_space_io,
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parent->address_space_io,
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cmd & PCI_COMMAND_IO);
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/* TODO: optinal VGA and VGA palette snooping support. */
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}
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static void pci_bridge_region_cleanup(PCIBridge *br)
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{
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PCIBus *parent = br->dev.bus;
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pci_bridge_cleanup_alias(&br->alias_io,
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parent->address_space_io);
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pci_bridge_cleanup_alias(&br->alias_mem,
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parent->address_space_mem);
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pci_bridge_cleanup_alias(&br->alias_pref_mem,
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parent->address_space_mem);
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}
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static void pci_bridge_update_mappings(PCIBridge *br)
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{
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/* Make updates atomic to: handle the case of one VCPU updating the bridge
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* while another accesses an unaffected region. */
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memory_region_transaction_begin();
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pci_bridge_region_cleanup(br);
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pci_bridge_region_init(br);
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memory_region_transaction_commit();
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}
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/* default write_config function for PCI-to-PCI bridge */
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void pci_bridge_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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PCIBridge *s = container_of(d, PCIBridge, dev);
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uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
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uint16_t newctl;
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pci_default_write_config(d, address, val, len);
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if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
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/* io base/limit */
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ranges_overlap(address, len, PCI_IO_BASE, 2) ||
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/* memory base/limit, prefetchable base/limit and
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io base/limit upper 16 */
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ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
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pci_bridge_update_mappings(s);
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}
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newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
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if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
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/* Trigger hot reset on 0->1 transition. */
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pci_bus_reset(&s->sec_bus);
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}
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}
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void pci_bridge_disable_base_limit(PCIDevice *dev)
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{
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uint8_t *conf = dev->config;
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pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
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PCI_IO_RANGE_MASK & 0xff);
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pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
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PCI_IO_RANGE_MASK & 0xff);
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pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
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PCI_MEMORY_RANGE_MASK & 0xffff);
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pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
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PCI_MEMORY_RANGE_MASK & 0xffff);
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pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
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PCI_PREF_RANGE_MASK & 0xffff);
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pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
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PCI_PREF_RANGE_MASK & 0xffff);
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pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
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pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
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}
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/* reset bridge specific configuration registers */
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void pci_bridge_reset_reg(PCIDevice *dev)
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{
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uint8_t *conf = dev->config;
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conf[PCI_PRIMARY_BUS] = 0;
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conf[PCI_SECONDARY_BUS] = 0;
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conf[PCI_SUBORDINATE_BUS] = 0;
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conf[PCI_SEC_LATENCY_TIMER] = 0;
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/*
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* the default values for base/limit registers aren't specified
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* in the PCI-to-PCI-bridge spec. So we don't thouch them here.
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* Each implementation can override it.
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* typical implementation does
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* zero base/limit registers or
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* disable forwarding: pci_bridge_disable_base_limit()
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* If disable forwarding is wanted, call pci_bridge_disable_base_limit()
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* after this function.
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*/
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pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
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PCI_IO_RANGE_MASK & 0xff);
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pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
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PCI_IO_RANGE_MASK & 0xff);
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pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
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PCI_MEMORY_RANGE_MASK & 0xffff);
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pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
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PCI_MEMORY_RANGE_MASK & 0xffff);
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pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
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PCI_PREF_RANGE_MASK & 0xffff);
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pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
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PCI_PREF_RANGE_MASK & 0xffff);
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pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
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pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
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pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
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}
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/* default reset function for PCI-to-PCI bridge */
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void pci_bridge_reset(DeviceState *qdev)
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{
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PCIDevice *dev = PCI_DEVICE(qdev);
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pci_bridge_reset_reg(dev);
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}
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/* default qdev initialization function for PCI-to-PCI bridge */
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int pci_bridge_initfn(PCIDevice *dev)
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{
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PCIBus *parent = dev->bus;
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PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
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PCIBus *sec_bus = &br->sec_bus;
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pci_set_word(dev->config + PCI_STATUS,
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PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
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pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
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dev->config[PCI_HEADER_TYPE] =
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(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
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PCI_HEADER_TYPE_BRIDGE;
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pci_set_word(dev->config + PCI_SEC_STATUS,
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PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
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qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev,
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br->bus_name);
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sec_bus->parent_dev = dev;
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sec_bus->map_irq = br->map_irq;
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sec_bus->address_space_mem = &br->address_space_mem;
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memory_region_init(&br->address_space_mem, "pci_bridge_pci", INT64_MAX);
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sec_bus->address_space_io = &br->address_space_io;
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memory_region_init(&br->address_space_io, "pci_bridge_io", 65536);
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pci_bridge_region_init(br);
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QLIST_INIT(&sec_bus->child);
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QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
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return 0;
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}
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/* default qdev clean up function for PCI-to-PCI bridge */
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int pci_bridge_exitfn(PCIDevice *pci_dev)
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{
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PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
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assert(QLIST_EMPTY(&s->sec_bus.child));
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QLIST_REMOVE(&s->sec_bus, sibling);
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pci_bridge_region_cleanup(s);
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memory_region_destroy(&s->address_space_mem);
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memory_region_destroy(&s->address_space_io);
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/* qbus_free() is called automatically by qdev_free() */
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return 0;
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}
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/*
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* before qdev initialization(qdev_init()), this function sets bus_name and
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* map_irq callback which are necessry for pci_bridge_initfn() to
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* initialize bus.
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*/
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void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
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pci_map_irq_fn map_irq)
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{
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br->map_irq = map_irq;
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br->bus_name = bus_name;
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}
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