371a775dc1
* 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu: qdev: Drop FROM_QBUS() macro isa: QOM'ify ISADevice isa: QOM'ify ISABus i8259: Convert PICCommonState to use QOM realizefn kvm/i8259: QOM'ify some more i8259: QOM'ify some more i8254: Convert PITCommonState to QOM realizefn kvm/i8254: QOM'ify some more i8254: QOM'ify some more isa: Use realizefn for ISADevice cs4231a: QOM'ify some more gus: QOM'ify some more
98 lines
3.4 KiB
C
98 lines
3.4 KiB
C
/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_SERIAL_H
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#define HW_SERIAL_H 1
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#include "hw/hw.h"
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#include "sysemu/sysemu.h"
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#include "exec/memory.h"
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#include "qemu/fifo8.h"
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#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
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struct SerialState {
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uint16_t divider;
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uint8_t rbr; /* receive register */
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uint8_t thr; /* transmit holding register */
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uint8_t tsr; /* transmit shift register */
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uint8_t ier;
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uint8_t iir; /* read only */
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uint8_t lcr;
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uint8_t mcr;
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uint8_t lsr; /* read only */
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uint8_t msr; /* read only */
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uint8_t scr;
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uint8_t fcr;
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uint8_t fcr_vmstate; /* we can't write directly this value
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it has side effects */
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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qemu_irq irq;
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CharDriverState *chr;
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int last_break_enable;
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int it_shift;
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int baudbase;
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int tsr_retry;
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uint32_t wakeup;
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/* Time when the last byte was successfully sent out of the tsr */
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uint64_t last_xmit_ts;
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Fifo8 recv_fifo;
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Fifo8 xmit_fifo;
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/* Interrupt trigger level for recv_fifo */
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uint8_t recv_fifo_itl;
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struct QEMUTimer *fifo_timeout_timer;
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int timeout_ipending; /* timeout interrupt pending state */
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uint64_t char_transmit_time; /* time to transmit a char in ticks */
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int poll_msl;
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struct QEMUTimer *modem_status_poll;
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MemoryRegion io;
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};
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extern const VMStateDescription vmstate_serial;
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extern const MemoryRegionOps serial_io_ops;
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void serial_realize_core(SerialState *s, Error **errp);
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void serial_exit_core(SerialState *s);
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void serial_set_frequency(SerialState *s, uint32_t frequency);
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/* legacy pre qom */
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SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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CharDriverState *chr, MemoryRegion *system_io);
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SerialState *serial_mm_init(MemoryRegion *address_space,
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hwaddr base, int it_shift,
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qemu_irq irq, int baudbase,
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CharDriverState *chr, enum device_endian end);
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/* serial-isa.c */
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#define TYPE_ISA_SERIAL "isa-serial"
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bool serial_isa_init(ISABus *bus, int index, CharDriverState *chr);
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#endif
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