9fe640a53d
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_prci model to hw/misc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/*
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* QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
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*
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_U_PRCI_H
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#define HW_SIFIVE_U_PRCI_H
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#define SIFIVE_U_PRCI_HFXOSCCFG 0x00
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#define SIFIVE_U_PRCI_COREPLLCFG0 0x04
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#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
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#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
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#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
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#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
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#define SIFIVE_U_PRCI_CORECLKSEL 0x24
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#define SIFIVE_U_PRCI_DEVICESRESET 0x28
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#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
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/*
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* Current FU540-C000 manual says ready bit is at bit 29, but
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* freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
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* We have to trust the actual code that works.
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*
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* see https://github.com/sifive/freedom-u540-c000-bootloader
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*/
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#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
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#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
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/* xxxPLLCFG0 register bits */
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#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
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#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
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#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
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#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
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#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
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/* xxxPLLCFG1 register bits */
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#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
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/* coreclksel register bits */
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#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
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#define SIFIVE_U_PRCI_REG_SIZE 0x1000
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#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
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#define SIFIVE_U_PRCI(obj) \
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OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI)
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typedef struct SiFiveUPRCIState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t hfxosccfg;
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uint32_t corepllcfg0;
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uint32_t ddrpllcfg0;
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uint32_t ddrpllcfg1;
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uint32_t gemgxlpllcfg0;
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uint32_t gemgxlpllcfg1;
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uint32_t coreclksel;
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uint32_t devicesreset;
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uint32_t clkmuxstatus;
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} SiFiveUPRCIState;
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/*
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* Clock indexes for use by Device Tree data and the PRCI driver.
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*
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* These values are from sifive-fu540-prci.h in the Linux kernel.
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*/
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#define PRCI_CLK_COREPLL 0
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#define PRCI_CLK_DDRPLL 1
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#define PRCI_CLK_GEMGXLPLL 2
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#define PRCI_CLK_TLCLK 3
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#endif /* HW_SIFIVE_U_PRCI_H */
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