713 lines
23 KiB
C
713 lines
23 KiB
C
/*
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* x86 exception helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/log.h"
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#include "sysemu/runstate.h"
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#include "exec/helper-proto.h"
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#include "helper-tcg.h"
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void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
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{
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raise_interrupt(env, intno, 1, 0, next_eip_addend);
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}
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void helper_raise_exception(CPUX86State *env, int exception_index)
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{
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raise_exception(env, exception_index);
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}
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/*
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* Check nested exceptions and change to double or triple fault if
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* needed. It should only be called, if this is not an interrupt.
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* Returns the new exception number.
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*/
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static int check_exception(CPUX86State *env, int intno, int *error_code,
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uintptr_t retaddr)
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{
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int first_contributory = env->old_exception == 0 ||
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(env->old_exception >= 10 &&
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env->old_exception <= 13);
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int second_contributory = intno == 0 ||
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(intno >= 10 && intno <= 13);
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qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
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env->old_exception, intno);
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#if !defined(CONFIG_USER_ONLY)
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if (env->old_exception == EXCP08_DBLE) {
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if (env->hflags & HF_GUEST_MASK) {
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cpu_vmexit(env, SVM_EXIT_SHUTDOWN, 0, retaddr); /* does not return */
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}
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qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return EXCP_HLT;
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}
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#endif
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if ((first_contributory && second_contributory)
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|| (env->old_exception == EXCP0E_PAGE &&
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(second_contributory || (intno == EXCP0E_PAGE)))) {
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intno = EXCP08_DBLE;
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*error_code = 0;
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}
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if (second_contributory || (intno == EXCP0E_PAGE) ||
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(intno == EXCP08_DBLE)) {
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env->old_exception = intno;
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}
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return intno;
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}
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/*
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* Signal an interruption. It is executed in the main CPU loop.
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* is_int is TRUE if coming from the int instruction. next_eip is the
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* env->eip value AFTER the interrupt instruction. It is only relevant if
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* is_int is TRUE.
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*/
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static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
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int is_int, int error_code,
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int next_eip_addend,
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uintptr_t retaddr)
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{
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CPUState *cs = env_cpu(env);
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if (!is_int) {
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cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
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error_code, retaddr);
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intno = check_exception(env, intno, &error_code, retaddr);
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} else {
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cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0, retaddr);
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}
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cs->exception_index = intno;
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env->error_code = error_code;
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env->exception_is_int = is_int;
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env->exception_next_eip = env->eip + next_eip_addend;
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cpu_loop_exit_restore(cs, retaddr);
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}
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/* shortcuts to generate exceptions */
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void QEMU_NORETURN raise_interrupt(CPUX86State *env, int intno, int is_int,
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int error_code, int next_eip_addend)
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{
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raise_interrupt2(env, intno, is_int, error_code, next_eip_addend, 0);
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}
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void raise_exception_err(CPUX86State *env, int exception_index,
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int error_code)
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{
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raise_interrupt2(env, exception_index, 0, error_code, 0, 0);
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}
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void raise_exception_err_ra(CPUX86State *env, int exception_index,
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int error_code, uintptr_t retaddr)
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{
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raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr);
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}
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void raise_exception(CPUX86State *env, int exception_index)
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{
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raise_interrupt2(env, exception_index, 0, 0, 0, 0);
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}
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void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr)
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{
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raise_interrupt2(env, exception_index, 0, 0, 0, retaddr);
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}
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#if !defined(CONFIG_USER_ONLY)
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static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint64_t ptep, pte;
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uint64_t exit_info_1 = 0;
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target_ulong pde_addr, pte_addr;
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uint32_t page_offset;
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int page_size;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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}
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if (!(env->nested_pg_mode & SVM_NPT_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (env->nested_pg_mode & SVM_NPT_PAE) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (env->nested_pg_mode & SVM_NPT_LMA) {
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uint64_t pml5e;
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uint64_t pml4e_addr, pml4e;
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pml5e = env->nested_cr3;
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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pml4e_addr = (pml5e & PG_ADDRESS_MASK) +
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(((gphys >> 39) & 0x1ff) << 3);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = (pml4e & PG_ADDRESS_MASK) +
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(((gphys >> 30) & 0x1ff) << 3);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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}
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if (pdpe & PG_PSE_MASK) {
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/* 1 GB page */
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page_size = 1024 * 1024 * 1024;
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pte_addr = pdpe_addr;
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pte = pdpe;
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goto do_check_protect;
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}
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} else
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#endif
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{
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pdpe_addr = (env->nested_cr3 & ~0x1f) + ((gphys >> 27) & 0x18);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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rsvd_mask |= PG_HI_USER_MASK;
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if (pdpe & (rsvd_mask | PG_NX_MASK)) {
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goto do_fault_rsvd;
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}
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pde_addr = (pdpe & PG_ADDRESS_MASK) + (((gphys >> 21) & 0x1ff) << 3);
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pde & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pde ^ PG_NX_MASK;
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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pte_addr = pde_addr;
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pte = pde;
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goto do_check_protect;
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}
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/* 4 KB page */
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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pte_addr = (pde & PG_ADDRESS_MASK) + (((gphys >> 12) & 0x1ff) << 3);
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pte = x86_ldq_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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/* combine pde and pte nx, user and rw protections */
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ptep &= pte ^ PG_NX_MASK;
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page_size = 4096;
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = (env->nested_cr3 & ~0xfff) + ((gphys >> 20) & 0xffc);
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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ptep = pde | PG_NX_MASK;
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/* if host cr4 PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (env->nested_pg_mode & SVM_NPT_PSE)) {
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page_size = 4096 * 1024;
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pte_addr = pde_addr;
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/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
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* Leave bits 20-13 in place for setting accessed/dirty bits below.
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*/
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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rsvd_mask = 0x200000;
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goto do_check_protect_pse36;
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}
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pde_addr, pde);
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}
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/* page directory entry */
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pte_addr = (pde & ~0xfff) + ((gphys >> 10) & 0xffc);
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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/* combine pde and pte user and rw protections */
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ptep &= pte | PG_NX_MASK;
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page_size = 4096;
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rsvd_mask = 0;
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}
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do_check_protect:
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rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
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do_check_protect_pse36:
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if (pte & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep ^= PG_NX_MASK;
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if (!(ptep & PG_USER_MASK)) {
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goto do_fault_protect;
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}
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if (ptep & PG_NX_MASK) {
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if (access_type == MMU_INST_FETCH) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_EXEC;
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}
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if (!(ptep & PG_RW_MASK)) {
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if (access_type == MMU_DATA_STORE) {
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goto do_fault_protect;
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}
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*prot &= ~PAGE_WRITE;
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}
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pte &= PG_ADDRESS_MASK & ~(page_size - 1);
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page_offset = gphys & (page_size - 1);
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return pte + page_offset;
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do_fault_rsvd:
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exit_info_1 |= SVM_NPTEXIT_RSVD;
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do_fault_protect:
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exit_info_1 |= SVM_NPTEXIT_P;
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do_fault:
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x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
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gphys);
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exit_info_1 |= SVM_NPTEXIT_US;
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if (access_type == MMU_DATA_STORE) {
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exit_info_1 |= SVM_NPTEXIT_RW;
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} else if (access_type == MMU_INST_FETCH) {
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exit_info_1 |= SVM_NPTEXIT_ID;
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}
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if (prot) {
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exit_info_1 |= SVM_NPTEXIT_GPA;
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} else { /* page table access */
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exit_info_1 |= SVM_NPTEXIT_GPT;
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}
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, env->retaddr);
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}
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/* return value:
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* -1 = cannot handle fault
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* 0 = nothing more to do
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* 1 = generate PF fault
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*/
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static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
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int is_write1, int mmu_idx)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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uint64_t ptep, pte;
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int32_t a20_mask;
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target_ulong pde_addr, pte_addr;
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int error_code = 0;
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int is_dirty, prot, page_size, is_write, is_user;
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hwaddr paddr;
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uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits);
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uint32_t page_offset;
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target_ulong vaddr;
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uint32_t pkr;
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is_user = mmu_idx == MMU_USER_IDX;
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#if defined(DEBUG_MMU)
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printf("MMU fault: addr=%" VADDR_PRIx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
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addr, is_write1, is_user, env->eip);
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#endif
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is_write = is_write1 & 1;
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a20_mask = x86_get_a20_mask(env);
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if (!(env->cr[0] & CR0_PG_MASK)) {
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pte = addr;
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#ifdef TARGET_X86_64
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if (!(env->hflags & HF_LMA_MASK)) {
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/* Without long mode we can only address 32bits in real mode */
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pte = (uint32_t)pte;
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}
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#endif
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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page_size = 4096;
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goto do_mapping;
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}
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if (!(env->efer & MSR_EFER_NXE)) {
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rsvd_mask |= PG_NX_MASK;
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}
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if (env->cr[4] & CR4_PAE_MASK) {
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uint64_t pde, pdpe;
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target_ulong pdpe_addr;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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bool la57 = env->cr[4] & CR4_LA57_MASK;
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uint64_t pml5e_addr, pml5e;
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uint64_t pml4e_addr, pml4e;
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int32_t sext;
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/* test virtual address sign extension */
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sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
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if (sext != 0 && sext != -1) {
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env->error_code = 0;
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cs->exception_index = EXCP0D_GPF;
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return 1;
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}
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if (la57) {
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pml5e_addr = ((env->cr[3] & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e_addr = get_hphys(cs, pml5e_addr, MMU_DATA_STORE, NULL);
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml5e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml5e & PG_ACCESSED_MASK)) {
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pml5e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml5e_addr, pml5e);
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}
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ptep = pml5e ^ PG_NX_MASK;
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} else {
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pml5e = env->cr[3];
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ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
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}
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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pml4e_addr = get_hphys(cs, pml4e_addr, MMU_DATA_STORE, false);
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pml4e & (rsvd_mask | PG_PSE_MASK)) {
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goto do_fault_rsvd;
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}
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if (!(pml4e & PG_ACCESSED_MASK)) {
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pml4e |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pml4e_addr, pml4e);
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}
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ptep &= pml4e ^ PG_NX_MASK;
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
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a20_mask;
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pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, NULL);
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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goto do_fault;
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}
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if (pdpe & rsvd_mask) {
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goto do_fault_rsvd;
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}
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ptep &= pdpe ^ PG_NX_MASK;
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if (!(pdpe & PG_ACCESSED_MASK)) {
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pdpe |= PG_ACCESSED_MASK;
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x86_stl_phys_notdirty(cs, pdpe_addr, pdpe);
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}
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if (pdpe & PG_PSE_MASK) {
|
|
/* 1 GB page */
|
|
page_size = 1024 * 1024 * 1024;
|
|
pte_addr = pdpe_addr;
|
|
pte = pdpe;
|
|
goto do_check_protect;
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
/* XXX: load them when cr3 is loaded ? */
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
a20_mask;
|
|
pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, false);
|
|
pdpe = x86_ldq_phys(cs, pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
goto do_fault;
|
|
}
|
|
rsvd_mask |= PG_HI_USER_MASK;
|
|
if (pdpe & (rsvd_mask | PG_NX_MASK)) {
|
|
goto do_fault_rsvd;
|
|
}
|
|
ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
|
|
}
|
|
|
|
pde_addr = ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
|
|
a20_mask;
|
|
pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
|
|
pde = x86_ldq_phys(cs, pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
goto do_fault;
|
|
}
|
|
if (pde & rsvd_mask) {
|
|
goto do_fault_rsvd;
|
|
}
|
|
ptep &= pde ^ PG_NX_MASK;
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
pte_addr = pde_addr;
|
|
pte = pde;
|
|
goto do_check_protect;
|
|
}
|
|
/* 4 KB page */
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
x86_stl_phys_notdirty(cs, pde_addr, pde);
|
|
}
|
|
pte_addr = ((pde & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
|
|
a20_mask;
|
|
pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
|
|
pte = x86_ldq_phys(cs, pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
goto do_fault;
|
|
}
|
|
if (pte & rsvd_mask) {
|
|
goto do_fault_rsvd;
|
|
}
|
|
/* combine pde and pte nx, user and rw protections */
|
|
ptep &= pte ^ PG_NX_MASK;
|
|
page_size = 4096;
|
|
} else {
|
|
uint32_t pde;
|
|
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
|
|
a20_mask;
|
|
pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
|
|
pde = x86_ldl_phys(cs, pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
goto do_fault;
|
|
}
|
|
ptep = pde | PG_NX_MASK;
|
|
|
|
/* if PSE bit is set, then we use a 4MB page */
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
page_size = 4096 * 1024;
|
|
pte_addr = pde_addr;
|
|
|
|
/* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
|
|
* Leave bits 20-13 in place for setting accessed/dirty bits below.
|
|
*/
|
|
pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
|
|
rsvd_mask = 0x200000;
|
|
goto do_check_protect_pse36;
|
|
}
|
|
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
x86_stl_phys_notdirty(cs, pde_addr, pde);
|
|
}
|
|
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
|
|
a20_mask;
|
|
pte_addr = get_hphys(cs, pte_addr, MMU_DATA_STORE, NULL);
|
|
pte = x86_ldl_phys(cs, pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
goto do_fault;
|
|
}
|
|
/* combine pde and pte user and rw protections */
|
|
ptep &= pte | PG_NX_MASK;
|
|
page_size = 4096;
|
|
rsvd_mask = 0;
|
|
}
|
|
|
|
do_check_protect:
|
|
rsvd_mask |= (page_size - 1) & PG_ADDRESS_MASK & ~PG_PSE_PAT_MASK;
|
|
do_check_protect_pse36:
|
|
if (pte & rsvd_mask) {
|
|
goto do_fault_rsvd;
|
|
}
|
|
ptep ^= PG_NX_MASK;
|
|
|
|
/* can the page can be put in the TLB? prot will tell us */
|
|
if (is_user && !(ptep & PG_USER_MASK)) {
|
|
goto do_fault_protect;
|
|
}
|
|
|
|
prot = 0;
|
|
if (mmu_idx != MMU_KSMAP_IDX || !(ptep & PG_USER_MASK)) {
|
|
prot |= PAGE_READ;
|
|
if ((ptep & PG_RW_MASK) || (!is_user && !(env->cr[0] & CR0_WP_MASK))) {
|
|
prot |= PAGE_WRITE;
|
|
}
|
|
}
|
|
if (!(ptep & PG_NX_MASK) &&
|
|
(mmu_idx == MMU_USER_IDX ||
|
|
!((env->cr[4] & CR4_SMEP_MASK) && (ptep & PG_USER_MASK)))) {
|
|
prot |= PAGE_EXEC;
|
|
}
|
|
|
|
if (!(env->hflags & HF_LMA_MASK)) {
|
|
pkr = 0;
|
|
} else if (ptep & PG_USER_MASK) {
|
|
pkr = env->cr[4] & CR4_PKE_MASK ? env->pkru : 0;
|
|
} else {
|
|
pkr = env->cr[4] & CR4_PKS_MASK ? env->pkrs : 0;
|
|
}
|
|
if (pkr) {
|
|
uint32_t pk = (pte & PG_PKRU_MASK) >> PG_PKRU_BIT;
|
|
uint32_t pkr_ad = (pkr >> pk * 2) & 1;
|
|
uint32_t pkr_wd = (pkr >> pk * 2) & 2;
|
|
uint32_t pkr_prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
|
|
|
if (pkr_ad) {
|
|
pkr_prot &= ~(PAGE_READ | PAGE_WRITE);
|
|
} else if (pkr_wd && (is_user || env->cr[0] & CR0_WP_MASK)) {
|
|
pkr_prot &= ~PAGE_WRITE;
|
|
}
|
|
|
|
prot &= pkr_prot;
|
|
if ((pkr_prot & (1 << is_write1)) == 0) {
|
|
assert(is_write1 != 2);
|
|
error_code |= PG_ERROR_PK_MASK;
|
|
goto do_fault_protect;
|
|
}
|
|
}
|
|
|
|
if ((prot & (1 << is_write1)) == 0) {
|
|
goto do_fault_protect;
|
|
}
|
|
|
|
/* yes, it can! */
|
|
is_dirty = is_write && !(pte & PG_DIRTY_MASK);
|
|
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
|
pte |= PG_ACCESSED_MASK;
|
|
if (is_dirty) {
|
|
pte |= PG_DIRTY_MASK;
|
|
}
|
|
x86_stl_phys_notdirty(cs, pte_addr, pte);
|
|
}
|
|
|
|
if (!(pte & PG_DIRTY_MASK)) {
|
|
/* only set write access if already dirty... otherwise wait
|
|
for dirty access */
|
|
assert(!is_write);
|
|
prot &= ~PAGE_WRITE;
|
|
}
|
|
|
|
do_mapping:
|
|
pte = pte & a20_mask;
|
|
|
|
/* align to page_size */
|
|
pte &= PG_ADDRESS_MASK & ~(page_size - 1);
|
|
page_offset = addr & (page_size - 1);
|
|
paddr = get_hphys(cs, pte + page_offset, is_write1, &prot);
|
|
|
|
/* Even if 4MB pages, we map only one 4KB page in the cache to
|
|
avoid filling it too fast */
|
|
vaddr = addr & TARGET_PAGE_MASK;
|
|
paddr &= TARGET_PAGE_MASK;
|
|
|
|
assert(prot & (1 << is_write1));
|
|
tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
|
|
prot, mmu_idx, page_size);
|
|
return 0;
|
|
do_fault_rsvd:
|
|
error_code |= PG_ERROR_RSVD_MASK;
|
|
do_fault_protect:
|
|
error_code |= PG_ERROR_P_MASK;
|
|
do_fault:
|
|
error_code |= (is_write << PG_ERROR_W_BIT);
|
|
if (is_user)
|
|
error_code |= PG_ERROR_U_MASK;
|
|
if (is_write1 == 2 &&
|
|
(((env->efer & MSR_EFER_NXE) &&
|
|
(env->cr[4] & CR4_PAE_MASK)) ||
|
|
(env->cr[4] & CR4_SMEP_MASK)))
|
|
error_code |= PG_ERROR_I_D_MASK;
|
|
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
|
|
/* cr2 is not modified in case of exceptions */
|
|
x86_stq_phys(cs,
|
|
env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
|
|
addr);
|
|
} else {
|
|
env->cr[2] = addr;
|
|
}
|
|
env->error_code = error_code;
|
|
cs->exception_index = EXCP0E_PAGE;
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
|
|
MMUAccessType access_type, int mmu_idx,
|
|
bool probe, uintptr_t retaddr)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* user mode only emulation */
|
|
env->cr[2] = addr;
|
|
env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT;
|
|
env->error_code |= PG_ERROR_U_MASK;
|
|
cs->exception_index = EXCP0E_PAGE;
|
|
env->exception_is_int = 0;
|
|
env->exception_next_eip = -1;
|
|
cpu_loop_exit_restore(cs, retaddr);
|
|
#else
|
|
env->retaddr = retaddr;
|
|
if (handle_mmu_fault(cs, addr, size, access_type, mmu_idx)) {
|
|
/* FIXME: On error in get_hphys we have already jumped out. */
|
|
g_assert(!probe);
|
|
raise_exception_err_ra(env, cs->exception_index,
|
|
env->error_code, retaddr);
|
|
}
|
|
return true;
|
|
#endif
|
|
}
|