qemu-e2k/target
Peter Maydell 85e7d1e9ff target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4.  QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.

We're going to add come in gen_update_fp_context() which relies on
the "always 4" property.  Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause.  Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
2021-09-21 16:28:27 +01:00
..
alpha target/alpha: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
arm target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration 2021-09-21 16:28:27 +01:00
avr Trivial patches pull request 20210916 2021-09-16 16:02:31 +01:00
cris target/cris: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
hexagon accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
hppa target/hppa: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
i386 hvf: Add Apple Silicon support 2021-09-20 09:57:03 +01:00
m68k Pull request linux-user 20210916 2021-09-16 21:09:18 +01:00
microblaze target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
mips target/mips: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
nios2 Pull request linux-user 20210916 2021-09-16 21:09:18 +01:00
openrisc target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
ppc target/ppc: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
riscv target/riscv: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
rx target/rx: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
s390x accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
sh4 target/sh4: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
sparc Trivial patches pull request 20210916 2021-09-16 16:02:31 +01:00
tricore accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
xtensa target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu 2021-09-14 12:00:21 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00