qemu-e2k/target/ppc
Frederic Barrat 609b1c8669 target/ppc: cpu_init: Clean up stop state on cpu reset
The 'resume_as_sreset' attribute of a cpu is set when a thread is
entering a stop state on ppc books. It causes the thread to be
re-routed to vector 0x100 when woken up by an exception. So it must be
cleared on reset or a thread might be re-routed unexpectedly after a
reset, when it was not in a stop state and/or when the appropriate
exception handler isn't set up yet.

Using skiboot, it can be tested by resetting the system when it is
quiet and most threads are idle and in stop state.

After the reset occurs, skiboot elects a primary thread and all the
others wait in secondary_wait. The primary thread does all the system
initialization from main_cpu_entry() and at some point, the
decrementer interrupt starts ticking. The exception vector for the
decrementer interrupt is in place, so that shouldn't be a
problem. However, if that primary thread was in stop state prior to
the reset, and because the resume_as_sreset parameters is still set,
it is re-routed to exception vector 0x100. Which, at that time, is
still defined as the entry point for BML. So that primary thread
restarts as new and ends up being treated like any other secondary
thread. All threads are now waiting in secondary_wait.

It results in a full system hang with no message on the console, as
the uart hasn't been init'ed yet. It's actually not obvious to realise
what's happening if not tracing reset (-d cpu_reset). The fix is
simply to clear the 'resume_as_sreset' attribute on reset.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220617095222.612212-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20 08:38:59 -03:00
..
translate target/ppc: Implemented vector module quadword 2022-06-20 08:38:58 -03:00
arch_dump.c
compat.c
cpu_init.c target/ppc: cpu_init: Clean up stop state on cpu reset 2022-06-20 08:38:59 -03:00
cpu-models.c
cpu-models.h
cpu-param.h
cpu-qom.h
cpu.c
cpu.h target/ppc: Implemented xvf16ger* 2022-05-26 17:11:33 -03:00
dfp_helper.c
excp_helper.c
fpu_helper.c target/ppc: fix unreachable code in fpu_helper.c 2022-06-20 08:38:58 -03:00
gdbstub.c
helper_regs.c target/ppc: Fix tlbie 2022-05-26 17:11:32 -03:00
helper_regs.h
helper.h target/ppc: Implemented vector module quadword 2022-06-20 08:38:58 -03:00
insn32.decode target/ppc: Implemented vector module quadword 2022-06-20 08:38:58 -03:00
insn64.decode target/ppc: Implemented [pm]xvbf16ger2* 2022-05-26 17:11:33 -03:00
int_helper.c target/ppc: avoid int32 multiply overflow in int_helper.c 2022-06-20 08:38:58 -03:00
internal.h target/ppc: Implemented xvi*ger* instructions 2022-05-26 17:11:33 -03:00
Kconfig
kvm_ppc.h
kvm-stub.c
kvm.c
machine.c target/ppc: Implement lwsync with weaker memory ordering 2022-05-26 17:11:33 -03:00
mem_helper.c
meson.build
misc_helper.c
mmu_common.c
mmu_helper.c
mmu-book3s-v3.c
mmu-book3s-v3.h
mmu-books.h
mmu-hash32.c
mmu-hash32.h
mmu-hash64.c
mmu-hash64.h
mmu-radix64.c
mmu-radix64.h
monitor.c
power8-pmu-regs.c.inc
power8-pmu.c
power8-pmu.h
spr_common.h
tcg-stub.c
timebase_helper.c
trace-events
trace.h
translate.c target/ppc: Implement lwsync with weaker memory ordering 2022-05-26 17:11:33 -03:00
user_only_helper.c