818b9f111d
Removal of register reset omitted initialization of CR4 guest/host mask.
x86_64 guests aren't booting without it.
Fixes: 5009ef22c6 ("i386: hvf: Don't duplicate register reset")
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Message-Id: <20200714090726.41082-1-r.bolshakov@yadro.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
237 lines
6.8 KiB
C
237 lines
6.8 KiB
C
/*
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* Copyright (C) 2016 Veertu Inc,
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* Copyright (C) 2017 Google Inc,
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* Based on Veertu vddh/vmm/vmx.h
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*
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* Interfaces to Hypervisor.framework to read/write X86 registers and VMCS.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* This file contain code under public domain from the hvdos project:
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* https://github.com/mist64/hvdos
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*/
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#ifndef VMX_H
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#define VMX_H
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#include <Hypervisor/hv.h>
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#include <Hypervisor/hv_vmx.h>
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#include "vmcs.h"
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#include "cpu.h"
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#include "x86.h"
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#include "exec/address-spaces.h"
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static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
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{
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uint64_t v;
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if (hv_vcpu_read_register(vcpu, reg, &v)) {
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abort();
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}
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return v;
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}
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/* write GPR */
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static inline void wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
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{
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if (hv_vcpu_write_register(vcpu, reg, v)) {
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abort();
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}
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}
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/* read VMCS field */
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static inline uint64_t rvmcs(hv_vcpuid_t vcpu, uint32_t field)
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{
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uint64_t v;
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hv_vmx_vcpu_read_vmcs(vcpu, field, &v);
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return v;
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}
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/* write VMCS field */
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static inline void wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
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{
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hv_vmx_vcpu_write_vmcs(vcpu, field, v);
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}
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/* desired control word constrained by hardware/hypervisor capabilities */
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static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl)
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{
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return (ctrl | (cap & 0xffffffff)) & (cap >> 32);
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}
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#define VM_ENTRY_GUEST_LMA (1LL << 9)
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#define AR_TYPE_ACCESSES_MASK 1
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#define AR_TYPE_READABLE_MASK (1 << 1)
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#define AR_TYPE_WRITEABLE_MASK (1 << 2)
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#define AR_TYPE_CODE_MASK (1 << 3)
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#define AR_TYPE_MASK 0x0f
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#define AR_TYPE_BUSY_64_TSS 11
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#define AR_TYPE_BUSY_32_TSS 11
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#define AR_TYPE_BUSY_16_TSS 3
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#define AR_TYPE_LDT 2
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static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
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{
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uint64_t entry_ctls;
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efer |= MSR_EFER_LMA;
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wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
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entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
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wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) |
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VM_ENTRY_GUEST_LMA);
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uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS);
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if ((efer & MSR_EFER_LME) &&
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(guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
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wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS,
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(guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
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}
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}
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static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
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{
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uint64_t entry_ctls;
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entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
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wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA);
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efer &= ~MSR_EFER_LMA;
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wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
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}
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static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
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{
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int i;
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uint64_t pdpte[4] = {0, 0, 0, 0};
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uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
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uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
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uint64_t changed_cr0 = old_cr0 ^ cr0;
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uint64_t mask = CR0_PG | CR0_CD | CR0_NW | CR0_NE | CR0_ET;
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uint64_t entry_ctls;
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if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
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!(efer & MSR_EFER_LME)) {
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address_space_read(&address_space_memory,
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rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
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MEMTXATTRS_UNSPECIFIED, pdpte, 32);
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/* Only set PDPTE when appropriate. */
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for (i = 0; i < 4; i++) {
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wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
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}
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}
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wvmcs(vcpu, VMCS_CR0_MASK, mask);
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wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);
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if (efer & MSR_EFER_LME) {
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if (changed_cr0 & CR0_PG) {
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if (cr0 & CR0_PG) {
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enter_long_mode(vcpu, cr0, efer);
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} else {
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exit_long_mode(vcpu, cr0, efer);
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}
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}
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} else {
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entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
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wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA);
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}
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/* Filter new CR0 after we are finished examining it above. */
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cr0 = (cr0 & ~(mask & ~CR0_PG));
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wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET);
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hv_vcpu_invalidate_tlb(vcpu);
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hv_vcpu_flush(vcpu);
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}
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static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
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{
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uint64_t guest_cr4 = cr4 | CR4_VMXE;
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wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4);
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wvmcs(vcpu, VMCS_CR4_SHADOW, cr4);
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wvmcs(vcpu, VMCS_CR4_MASK, CR4_VMXE);
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hv_vcpu_invalidate_tlb(vcpu);
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hv_vcpu_flush(vcpu);
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}
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static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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uint64_t val;
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/* BUG, should take considering overlap.. */
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wreg(cpu->hvf_fd, HV_X86_RIP, rip);
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env->eip = rip;
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/* after moving forward in rip, we need to clean INTERRUPTABILITY */
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val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
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if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
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VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
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env->hflags &= ~HF_INHIBIT_IRQ_MASK;
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wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY,
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val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
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VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
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}
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}
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static inline void vmx_clear_nmi_blocking(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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env->hflags2 &= ~HF2_NMI_MASK;
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uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
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gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
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wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
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}
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static inline void vmx_set_nmi_blocking(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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env->hflags2 |= HF2_NMI_MASK;
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uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
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gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
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wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
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}
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static inline void vmx_set_nmi_window_exiting(CPUState *cpu)
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{
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uint64_t val;
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val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
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wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val |
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VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
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}
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static inline void vmx_clear_nmi_window_exiting(CPUState *cpu)
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{
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uint64_t val;
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val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
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wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val &
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~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
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}
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#endif
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