277 lines
8.1 KiB
C
277 lines
8.1 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "hw/ppc/xics.h"
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#include "hw/ppc/xics_spapr.h"
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#include "hw/ppc/fdt.h"
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#include "qapi/visitor.h"
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/*
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* Guest interfaces
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*/
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static target_ulong h_cppr(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong cppr = args[0];
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icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
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return H_SUCCESS;
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}
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static target_ulong h_ipi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong mfrr = args[1];
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ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
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if (!icp) {
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return H_PARAMETER;
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}
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icp_set_mfrr(icp, mfrr);
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return H_SUCCESS;
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}
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static target_ulong h_xirr(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
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args[0] = xirr;
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return H_SUCCESS;
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}
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static target_ulong h_xirr_x(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
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args[0] = xirr;
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args[1] = cpu_get_host_ticks();
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return H_SUCCESS;
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}
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static target_ulong h_eoi(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong xirr = args[0];
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icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
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return H_SUCCESS;
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}
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static target_ulong h_ipoll(PowerPCCPU *cpu, SpaprMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
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uint32_t mfrr;
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uint32_t xirr;
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if (!icp) {
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return H_PARAMETER;
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}
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xirr = icp_ipoll(icp, &mfrr);
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args[0] = xirr;
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args[1] = mfrr;
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return H_SUCCESS;
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}
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static void rtas_set_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->ics;
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uint32_t nr, srcno, server, priority;
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if ((nargs != 3) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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if (!ics) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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server = rtas_ld(args, 1);
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priority = rtas_ld(args, 2);
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if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
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|| (priority > 0xff)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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srcno = nr - ics->offset;
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ics_simple_write_xive(ics, srcno, server, priority, priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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static void rtas_get_xive(PowerPCCPU *cpu, SpaprMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->ics;
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uint32_t nr, srcno;
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if ((nargs != 1) || (nret != 3)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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if (!ics) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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srcno = nr - ics->offset;
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rtas_st(rets, 1, ics->irqs[srcno].server);
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rtas_st(rets, 2, ics->irqs[srcno].priority);
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}
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static void rtas_int_off(PowerPCCPU *cpu, SpaprMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->ics;
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uint32_t nr, srcno;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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if (!ics) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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srcno = nr - ics->offset;
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ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
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ics->irqs[srcno].priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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static void rtas_int_on(PowerPCCPU *cpu, SpaprMachineState *spapr,
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uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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ICSState *ics = spapr->ics;
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uint32_t nr, srcno;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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if (!ics) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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return;
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}
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srcno = nr - ics->offset;
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ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
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ics->irqs[srcno].saved_priority,
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ics->irqs[srcno].saved_priority);
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rtas_st(rets, 0, RTAS_OUT_SUCCESS);
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}
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void xics_spapr_init(SpaprMachineState *spapr)
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{
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/* Registration of global state belongs into realize */
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spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
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spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
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spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
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spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
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spapr_register_hypercall(H_CPPR, h_cppr);
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spapr_register_hypercall(H_IPI, h_ipi);
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spapr_register_hypercall(H_XIRR, h_xirr);
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spapr_register_hypercall(H_XIRR_X, h_xirr_x);
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spapr_register_hypercall(H_EOI, h_eoi);
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spapr_register_hypercall(H_IPOLL, h_ipoll);
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}
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void spapr_dt_xics(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
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uint32_t phandle)
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{
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uint32_t interrupt_server_ranges_prop[] = {
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0, cpu_to_be32(nr_servers),
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};
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int node;
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_FDT(node = fdt_add_subnode(fdt, 0, XICS_NODENAME));
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_FDT(fdt_setprop_string(fdt, node, "device_type",
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"PowerPC-External-Interrupt-Presentation"));
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_FDT(fdt_setprop_string(fdt, node, "compatible", "IBM,ppc-xicp"));
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_FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
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_FDT(fdt_setprop(fdt, node, "ibm,interrupt-server-ranges",
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interrupt_server_ranges_prop,
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sizeof(interrupt_server_ranges_prop)));
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_FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
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_FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
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_FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
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}
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