qemu-e2k/target
Taylor Simpson 8872533671 Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions
Previously the store-conditional code was writing to hex_pred[prednum].
Then, the fGEN_TCG override was reading from there to the destination
variable so that the packet commit logic would handle it properly.

The correct implementation is to write to the destination variable
and don't have the extra read in the override.

Remove the unused arguments from gen_store_conditional[48]

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-4-git-send-email-tsimpson@quicinc.com>
2021-06-29 11:32:50 -05:00
..
alpha target/alpha: Honor the FEN bit 2021-06-28 07:27:55 -07:00
arm target/arm: Implement MTE3 2021-06-24 14:58:48 +01:00
avr
cris
hexagon Hexagon (target/hexagon) cleanup gen_store_conditional[48] functions 2021-06-29 11:32:50 -05:00
hppa tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode 2021-06-19 08:51:11 -07:00
i386 target/i386: kvm: add support for TSC scaling 2021-06-25 10:53:46 +02:00
m68k tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode 2021-06-19 08:51:11 -07:00
microblaze
mips target/mips: Merge msa32/msa64 decodetree definitions 2021-06-24 16:48:08 +02:00
nios2
openrisc
ppc tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode 2021-06-19 08:51:11 -07:00
riscv target/riscv: gdbstub: Fix dynamic CSR XML generation 2021-06-24 05:00:12 -07:00
rx
s390x target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub 2021-06-21 08:48:21 +02:00
sh4
sparc
tricore
xtensa
meson.build