f7a9e80d5b
Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-20-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This program generates the semantics file that is processed by
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* the do_qemu.py script. We use the C preporcessor to manipulate the
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* files imported from the Hexagon architecture library.
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*/
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#include <stdio.h>
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#define STRINGIZE(X) #X
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int main(int argc, char *argv[])
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{
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FILE *outfile;
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if (argc != 2) {
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fprintf(stderr, "Usage: gen_semantics ouptputfile\n");
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return 1;
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}
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outfile = fopen(argv[1], "w");
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if (outfile == NULL) {
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fprintf(stderr, "Cannot open %s for writing\n", argv[1]);
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return 1;
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}
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/*
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* Process the instruction definitions
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* Scalar core instructions have the following form
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* Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
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* "Add 32-bit registers",
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* { RdV=RsV+RtV;})
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*/
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#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
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do { \
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fprintf(outfile, "SEMANTICS( \\\n" \
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" \"%s\", \\\n" \
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" %s, \\\n" \
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" \"\"\"%s\"\"\" \\\n" \
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")\n", \
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#TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \
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fprintf(outfile, "ATTRIBUTES( \\\n" \
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" \"%s\", \\\n" \
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" \"%s\" \\\n" \
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")\n", \
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#TAG, STRINGIZE(ATTRIBS)); \
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} while (0);
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#include "imported/allidefs.def"
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#undef Q6INSN
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/*
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* Process the macro definitions
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* Macros definitions have the following form
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* DEF_MACRO(
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* fLSBNEW0,
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* predlog_read(thread,0),
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* ()
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* )
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* The important part here is the attributes. Whenever an instruction
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* invokes a macro, we add the macro's attributes to the instruction.
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*/
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#define DEF_MACRO(MNAME, BEH, ATTRS) \
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fprintf(outfile, "MACROATTRIB( \\\n" \
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" \"%s\", \\\n" \
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" \"\"\"%s\"\"\", \\\n" \
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" \"%s\" \\\n" \
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")\n", \
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#MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS));
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#include "imported/macros.def"
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#undef DEF_MACRO
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fclose(outfile);
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return 0;
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}
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