Yongbok Kim 99029be1c2 target/mips: Add implementation of GINVT instruction ... Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>		2020-01-29 19:28:52 +01:00
..
libvixl	libvixl: remove per-target compiler flags	2019-12-17 19:32:48 +01:00
alpha.c
arm-a64.cc
arm.c
cris.c	cris: do not leak struct cris_disasm_data	2019-10-04 18:49:17 +02:00
hppa.c
i386.c
lm32.c
m68k.c
Makefile.objs
microblaze.c
mips.c	target/mips: Add implementation of GINVT instruction	2020-01-29 19:28:52 +01:00
moxie.c
nanomips.cpp
nanomips.h
nios2.c
ppc.c	ppc: Add support for 'mffsl' instruction	2019-08-21 17:17:39 +10:00
riscv.c	disas/riscv: Fix rdinstreth constraint	2019-06-27 02:47:04 -07:00
s390.c
sh4.c
sparc.c
tci.c
xtensa.c