Bin Meng 898dc008e8 hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card ... Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=icicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-09-09 15:54:18 -07:00
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boot.c
Kconfig	hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card	2020-09-09 15:54:18 -07:00
meson.build	hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board	2020-09-09 15:54:18 -07:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card	2020-09-09 15:54:18 -07:00
numa.c
opentitan.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
riscv_htif.c
sifive_clint.c
sifive_e_prci.c
sifive_e.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
sifive_gpio.c
sifive_plic.c
sifive_test.c	riscv: sifive_test: Allow 16-bit writes to memory region	2020-09-09 15:54:18 -07:00
sifive_u_otp.c
sifive_u_prci.c
sifive_u.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
sifive_uart.c
spike.c	hw/riscv: spike: Allow creating multiple NUMA sockets	2020-08-25 09:11:35 -07:00
trace-events
trace.h
virt.c	hw/riscv: virt: Allow creating multiple NUMA sockets	2020-08-25 09:11:35 -07:00