qemu-e2k/target/arm
Peter Maydell e784807cd2 target/arm: Do hflags rebuild in cpsr_write()
Currently we rely on all the callsites of cpsr_write() to rebuild the
cached hflags if they change one of the CPSR bits which we use as a
TB flag and cache in hflags.  This is a bit awkward when we want to
change the set of CPSR bits that we cache, because it means we need
to re-audit all the cpsr_write() callsites to see which flags they
are writing and whether they now need to rebuild the hflags.

Switch instead to making cpsr_write() call arm_rebuild_hflags()
itself if one of the bits being changed is a cached bit.

We don't do the rebuild for the CPSRWriteRaw write type, because that
kind of write is generally doing something special anyway.  For the
CPSRWriteRaw callsites in the KVM code and inbound migration we
definitely don't want to recalculate the hflags; the callsites in
boot.c and arm-powerctl.c have to do a rebuild-hflags call themselves
anyway because of other CPU state changes they make.

This allows us to drop explicit arm_rebuild_hflags() calls in a
couple of places where the only reason we needed to call it was the
CPSR write.

This fixes a bug where we were incorrectly failing to rebuild hflags
in the code path for a gdbstub write to CPSR, which meant that you
could make QEMU assert by breaking into a running guest, altering the
CPSR to change the value of, for example, CPSR.E, and then
continuing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210817201843.3829-1-peter.maydell@linaro.org
2021-08-26 17:02:01 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c target/arm/cpu64: Validate sve vector lengths are supported 2021-08-26 17:01:59 +01:00
cpu_tcg.c target/arm: Implement debug_check_breakpoint 2021-07-21 07:47:04 -10:00
cpu-param.h
cpu-qom.h
cpu.c target/arm: Avoid assertion trying to use KVM and multiple ASes 2021-08-26 17:02:01 +01:00
cpu.h target/arm: Do hflags rebuild in cpsr_write() 2021-08-26 17:02:01 +01:00
crypto_helper.c
debug_helper.c accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
gdbstub64.c
gdbstub.c target/arm: Enforce that M-profile SP low 2 bits are always zero 2021-07-27 10:57:39 +01:00
helper-a64.c tcg: Rename helper_atomic_*_mmu and provide for user-only 2021-07-21 07:45:38 -10:00
helper-a64.h
helper-mve.h target/arm: Implement MVE interleaving loads/stores 2021-08-25 10:48:50 +01:00
helper-sve.h
helper.c target/arm: Do hflags rebuild in cpsr_write() 2021-08-26 17:02:01 +01:00
helper.h target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
idau.h
internals.h target/arm: Export aarch64_sve_zcr_get_valid_len 2021-07-27 10:57:40 +01:00
iwmmxt_helper.c
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm64.c target/arm/kvm64: Ensure sve vls map is completely clear 2021-08-26 17:01:59 +01:00
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() 2021-08-25 10:48:50 +01:00
m_helper.c target/arm: Implement M-profile trapping on division by zero 2021-08-25 10:48:50 +01:00
m-nocp.decode
machine.c
meson.build target/arm: Implement MVE VLDR/VSTR (non-widening forms) 2021-06-21 16:49:38 +01:00
monitor.c
mte_helper.c target/arm: Implement MTE3 2021-06-24 14:58:48 +01:00
mve_helper.c target/arm: Implement MVE interleaving loads/stores 2021-08-25 10:48:50 +01:00
mve.decode target/arm: Implement MVE interleaving loads/stores 2021-08-25 10:48:50 +01:00
neon_helper.c
neon-dp.decode
neon-ls.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
neon-shared.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
op_addsub.h
op_helper.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
pauth_helper.c
psci.c
sve_helper.c
sve.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
syndrome.h target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
t16.decode
t32.decode target/arm: Implement MVE VCTP 2021-08-25 10:48:50 +01:00
tlb_helper.c
trace-events
trace.h
translate-a32.h target/arm: Implement MVE VCTP 2021-08-25 10:48:50 +01:00
translate-a64.c accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
translate-a64.h
translate-m-nocp.c target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() 2021-06-21 16:49:38 +01:00
translate-mve.c target/arm: Implement MVE interleaving loads/stores 2021-08-25 10:48:50 +01:00
translate-neon.c target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
translate-sve.c target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
translate-vfp.c target/arm: Implement MVE VMOV to/from 2 general-purpose registers 2021-08-25 10:48:50 +01:00
translate.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
translate.h target/arm: Implement MVE shifts by register 2021-07-02 11:48:38 +01:00
vec_helper.c target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vec_internal.h target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vfp_helper.c target/arm: Check NaN mode before silencing NaN 2021-07-02 11:48:36 +01:00
vfp-uncond.decode
vfp.decode