63011373ad
* Add support for the max CPU * Detect user choice in TCG * Clear CSR values at reset and sync MPSTATE with host * Fix the typo of inverted order of pmpaddr13 and pmpaddr14 * Split TCG/KVM accelerators from cpu.c * Add extension properties for all cpus * Replace GDB exit calls with proper shutdown * Support KVM_GET_REG_LIST * Remove RVG warning * Use env_archcpu for better performance * Deprecate capital 'Z' CPU properties * Fix vfwmaccbf16.vf -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmUncYAACgkQr3yVEwxT gBPQ3g/9Fi4uYRK7dymHHAQbOO9NPlmVPPSxmQ8fNUhoZUkbHfm56JEl42Xr02rA Lg2ORRQxJhAinANV8CotnbyLRHNCAvouCMCQEjHo1YEHzdXc0tQzp+rIOHT7v9rH 6OQpI6RuCjO+0LQPMgzJx8yokMw/9b0uma3+RkNKod1XsSySo6JvDkMZGGZZWuVX Que3TMHzc4513PWEwRS9NaAHqRdy/ax0aPu9khswTYBxeJ/mBTLvGj4wBq5wnS7+ JPvq0M5ScUMl4K5o884wsAzOdxRk8QZOMx3duMCbqXw0xFmYZj/EzcIeHdnXwuDB lcANd6LcESMNUb8iDBaFRjLnZ/gNiu20/P/LPWyTirfoZXzZ+h6WPnSeli36xtzO KKWtvS1YggCjsDvh9/PLYAvUGBcS/kUhIynN10YKnoKB+wSDxxyvBS1GU6c8czgc WDf3V4P3Z8oPKDA/24Qd9Uiho1Gq9FED4eBQPb9PuvkfboKE/g7lUp708XXDFVld hkJMsYROSRvk54RHITrD9Z+XFQ2TfC8wHLH0IwlyynQnc1sKvXaR6U1hZTAVtE4f yley/xCQ7OUV+hrx1sQLURcN6A+SPummOY5jdHiD29QcJnOZnkSy5j2KOlnHSa5i 6v/6EFCgxwr69N6Q6X34VDv6+DZqLO2dNncQCInYFfupRhQ7t1E= =SUon -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20231012-1' of https://github.com/alistair23/qemu into staging Second RISC-V PR for 8.2 * Add support for the max CPU * Detect user choice in TCG * Clear CSR values at reset and sync MPSTATE with host * Fix the typo of inverted order of pmpaddr13 and pmpaddr14 * Split TCG/KVM accelerators from cpu.c * Add extension properties for all cpus * Replace GDB exit calls with proper shutdown * Support KVM_GET_REG_LIST * Remove RVG warning * Use env_archcpu for better performance * Deprecate capital 'Z' CPU properties * Fix vfwmaccbf16.vf # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmUncYAACgkQr3yVEwxT # gBPQ3g/9Fi4uYRK7dymHHAQbOO9NPlmVPPSxmQ8fNUhoZUkbHfm56JEl42Xr02rA # Lg2ORRQxJhAinANV8CotnbyLRHNCAvouCMCQEjHo1YEHzdXc0tQzp+rIOHT7v9rH # 6OQpI6RuCjO+0LQPMgzJx8yokMw/9b0uma3+RkNKod1XsSySo6JvDkMZGGZZWuVX # Que3TMHzc4513PWEwRS9NaAHqRdy/ax0aPu9khswTYBxeJ/mBTLvGj4wBq5wnS7+ # JPvq0M5ScUMl4K5o884wsAzOdxRk8QZOMx3duMCbqXw0xFmYZj/EzcIeHdnXwuDB # lcANd6LcESMNUb8iDBaFRjLnZ/gNiu20/P/LPWyTirfoZXzZ+h6WPnSeli36xtzO # KKWtvS1YggCjsDvh9/PLYAvUGBcS/kUhIynN10YKnoKB+wSDxxyvBS1GU6c8czgc # WDf3V4P3Z8oPKDA/24Qd9Uiho1Gq9FED4eBQPb9PuvkfboKE/g7lUp708XXDFVld # hkJMsYROSRvk54RHITrD9Z+XFQ2TfC8wHLH0IwlyynQnc1sKvXaR6U1hZTAVtE4f # yley/xCQ7OUV+hrx1sQLURcN6A+SPummOY5jdHiD29QcJnOZnkSy5j2KOlnHSa5i # 6v/6EFCgxwr69N6Q6X34VDv6+DZqLO2dNncQCInYFfupRhQ7t1E= # =SUon # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Oct 2023 00:09:36 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20231012-1' of https://github.com/alistair23/qemu: (54 commits) target/riscv: Fix vfwmaccbf16.vf target/riscv: deprecate capital 'Z' CPU properties target/riscv: Use env_archcpu for better performance target/riscv/tcg: remove RVG warning target/riscv/kvm: support KVM_GET_REG_LIST target/riscv/kvm: improve 'init_multiext_cfg' error msg gdbstub: replace exit calls with proper shutdown for softmmu hw/char: riscv_htif: replace exit calls with proper shutdown hw/misc/sifive_test.c: replace exit calls with proper shutdown softmmu: pass the main loop status to gdb "Wxx" packet softmmu: add means to pass an exit code when requesting a shutdown target/riscv/tcg-cpu.c: add extension properties for all cpus target/riscv: add riscv_cpu_get_name() target/riscv/cpu: move priv spec functions to tcg-cpu.c target/riscv/cpu.c: export isa_edata_arr[] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c target/riscv/cpu.c: make misa_ext_cfgs[] 'const' target/riscv/tcg: introduce tcg_cpu_instance_init() target/riscv/cpu.c: export set_misa() target/riscv/kvm: do not use riscv_cpu_add_misa_properties() ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> |
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| .. | ||
| _templates | ||
| about | ||
| config | ||
| devel | ||
| interop | ||
| specs | ||
| sphinx | ||
| sphinx-static | ||
| spin | ||
| system | ||
| tools | ||
| user | ||
| block-replication.txt | ||
| bypass-iommu.txt | ||
| COLO-FT.txt | ||
| colo-proxy.txt | ||
| conf.py | ||
| defs.rst.inc | ||
| igd-assign.txt | ||
| image-fuzzer.txt | ||
| index.rst | ||
| memory-hotplug.txt | ||
| meson.build | ||
| multi-thread-compression.txt | ||
| multiseat.txt | ||
| nvdimm.txt | ||
| pci_expander_bridge.txt | ||
| pcie_pci_bridge.txt | ||
| pcie_sriov.txt | ||
| pcie.txt | ||
| pvrdma.txt | ||
| qcow2-cache.txt | ||
| qdev-device-use.txt | ||
| qemu-option-trace.rst.inc | ||
| qemupciserial.inf | ||
| rdma.txt | ||
| spice-port-fqdn.txt | ||
| throttle.txt | ||
| xbzrle.txt | ||
| xen-save-devices-state.txt | ||