204 lines
6.5 KiB
C
204 lines
6.5 KiB
C
/*
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* QTest testcase for Q35 northbridge
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*
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* Copyright (c) 2015 Red Hat, Inc.
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*
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* Author: Gerd Hoffmann <kraxel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest.h"
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#include "libqos/pci.h"
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#include "libqos/pci-pc.h"
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#include "hw/pci-host/q35.h"
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#define TSEG_SIZE_TEST_GUEST_RAM_MBYTES 128
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/* @esmramc_tseg_sz: ESMRAMC.TSEG_SZ bitmask for selecting the requested TSEG
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* size. Must be a subset of
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* MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK.
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*
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* @extended_tseg_mbytes: Size of the extended TSEG. Only consulted if
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* @esmramc_tseg_sz equals
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* MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK precisely.
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*
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* @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes,
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* matching @esmramc_tseg_sz and @extended_tseg_mbytes
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* above.
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*/
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struct TsegSizeArgs {
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uint8_t esmramc_tseg_sz;
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uint16_t extended_tseg_mbytes;
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uint16_t expected_tseg_mbytes;
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};
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typedef struct TsegSizeArgs TsegSizeArgs;
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static const TsegSizeArgs tseg_1mb = {
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.esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB,
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.extended_tseg_mbytes = 0,
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.expected_tseg_mbytes = 1,
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};
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static const TsegSizeArgs tseg_2mb = {
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.esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB,
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.extended_tseg_mbytes = 0,
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.expected_tseg_mbytes = 2,
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};
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static const TsegSizeArgs tseg_8mb = {
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.esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB,
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.extended_tseg_mbytes = 0,
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.expected_tseg_mbytes = 8,
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};
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static const TsegSizeArgs tseg_ext_16mb = {
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.esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK,
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.extended_tseg_mbytes = 16,
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.expected_tseg_mbytes = 16,
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};
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static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
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{
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uint8_t smram;
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smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
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if (enabled) {
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smram |= mask;
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} else {
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smram &= ~mask;
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}
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qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram);
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}
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static bool smram_test_bit(QPCIDevice *pcidev, uint8_t mask)
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{
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uint8_t smram;
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smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
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return smram & mask;
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}
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static void test_smram_lock(void)
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{
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QPCIBus *pcibus;
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QPCIDevice *pcidev;
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QDict *response;
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qtest_start("-M q35");
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pcibus = qpci_init_pc(NULL);
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g_assert(pcibus != NULL);
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pcidev = qpci_device_find(pcibus, 0);
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g_assert(pcidev != NULL);
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/* check open is settable */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
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/* lock, check open is cleared & not settable */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_LCK, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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/* reset */
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response = qmp("{'execute': 'system_reset', 'arguments': {} }");
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g_assert(response);
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g_assert(!qdict_haskey(response, "error"));
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QDECREF(response);
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/* check open is settable again */
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
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smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
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g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
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g_free(pcidev);
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qpci_free_pc(pcibus);
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qtest_end();
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}
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static void test_tseg_size(const void *data)
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{
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const TsegSizeArgs *args = data;
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char *cmdline;
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QPCIBus *pcibus;
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QPCIDevice *pcidev;
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uint8_t smram_val;
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uint8_t esmramc_val;
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uint32_t ram_offs;
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if (args->esmramc_tseg_sz == MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
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cmdline = g_strdup_printf("-M q35 -m %uM "
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"-global mch.extended-tseg-mbytes=%u",
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TSEG_SIZE_TEST_GUEST_RAM_MBYTES,
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args->extended_tseg_mbytes);
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} else {
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cmdline = g_strdup_printf("-M q35 -m %uM",
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TSEG_SIZE_TEST_GUEST_RAM_MBYTES);
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}
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qtest_start(cmdline);
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g_free(cmdline);
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/* locate the DRAM controller */
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pcibus = qpci_init_pc(NULL);
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g_assert(pcibus != NULL);
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pcidev = qpci_device_find(pcibus, 0);
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g_assert(pcidev != NULL);
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/* Set TSEG size. Restrict TSEG visibility to SMM by setting T_EN. */
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esmramc_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_ESMRAMC);
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esmramc_val &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
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esmramc_val |= args->esmramc_tseg_sz;
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esmramc_val |= MCH_HOST_BRIDGE_ESMRAMC_T_EN;
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qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_ESMRAMC, esmramc_val);
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/* Enable TSEG by setting G_SMRAME. Close TSEG by setting D_CLS. */
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smram_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
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smram_val &= ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN |
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MCH_HOST_BRIDGE_SMRAM_D_LCK);
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smram_val |= (MCH_HOST_BRIDGE_SMRAM_D_CLS |
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MCH_HOST_BRIDGE_SMRAM_G_SMRAME);
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qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
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/* lock TSEG */
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smram_val |= MCH_HOST_BRIDGE_SMRAM_D_LCK;
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qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
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/* Now check that the byte right before the TSEG is r/w, and that the first
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* byte in the TSEG always reads as 0xff.
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*/
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ram_offs = (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mbytes) *
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1024 * 1024 - 1;
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g_assert_cmpint(readb(ram_offs), ==, 0);
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writeb(ram_offs, 1);
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g_assert_cmpint(readb(ram_offs), ==, 1);
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ram_offs++;
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g_assert_cmpint(readb(ram_offs), ==, 0xff);
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writeb(ram_offs, 1);
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g_assert_cmpint(readb(ram_offs), ==, 0xff);
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g_free(pcidev);
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qpci_free_pc(pcibus);
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qtest_end();
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}
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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qtest_add_func("/q35/smram/lock", test_smram_lock);
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qtest_add_data_func("/q35/tseg-size/1mb", &tseg_1mb, test_tseg_size);
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qtest_add_data_func("/q35/tseg-size/2mb", &tseg_2mb, test_tseg_size);
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qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size);
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qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb,
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test_tseg_size);
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return g_test_run();
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}
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