qemu-e2k/target
Peter Maydell b698e4eef5 arm: Allow system registers for KVM guests to be changed by QEMU code
At the moment the Arm implementations of kvm_arch_{get,put}_registers()
don't support having QEMU change the values of system registers
(aka coprocessor registers for AArch32). This is because although
kvm_arch_get_registers() calls write_list_to_cpustate() to
update the CPU state struct fields (so QEMU code can read the
values in the usual way), kvm_arch_put_registers() does not
call write_cpustate_to_list(), meaning that any changes to
the CPU state struct fields will not be passed back to KVM.

The rationale for this design is documented in a comment in the
AArch32 kvm_arch_put_registers() -- writing the values in the
cpregs list into the CPU state struct is "lossy" because the
write of a register might not succeed, and so if we blindly
copy the CPU state values back again we will incorrectly
change register values for the guest. The assumption was that
no QEMU code would need to write to the registers.

However, when we implemented debug support for KVM guests, we
broke that assumption: the code to handle "set the guest up
to take a breakpoint exception" does so by updating various
guest registers including ESR_EL1.

Support this by making kvm_arch_put_registers() synchronize
CPU state back into the list. We sync only those registers
where the initial write succeeds, which should be sufficient.

This commit is the same as commit 823e1b3818 which we
had to revert in commit 942f99c825, except that the bug
which was preventing EDK2 guest firmware running has been fixed:
kvm_arm_reset_vcpu() now calls write_list_to_cpustate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Eric Auger <eric.auger@redhat.com>
2019-05-07 12:55:02 +01:00
..
alpha tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
arm arm: Allow system registers for KVM guests to be changed by QEMU code 2019-05-07 12:55:02 +01:00
cris tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
hppa target/hppa: Always return EXCP_DMAR for protection id trap 2019-04-29 14:43:39 -07:00
i386 Add tcg_gen_extract2_*. 2019-04-28 11:43:10 +01:00
lm32 tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
m68k tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
microblaze tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
mips tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
moxie tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
nios2 Add Nios II semihosting support. 2019-04-29 16:09:51 +01:00
openrisc tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
ppc Add tcg_gen_extract2_*. 2019-04-28 11:43:10 +01:00
riscv tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
s390x Add tcg_gen_extract2_*. 2019-04-28 11:43:10 +01:00
sh4 tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
sparc tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
tilegx tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
tricore tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
unicore32 tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00
xtensa tcg: Hoist max_insns computation to tb_gen_code 2019-04-24 13:04:33 -07:00