Keith Packard ae4a70c071 riscv: Separate FPU register size from core register size in gdbstub [v2] ... The size of the FPU registers is dictated by the 'f' and 'd' features, not the core processor register size. Processors with the 'd' feature have 64-bit FPU registers. Processors without the 'd' feature but with the 'f' feature have 32-bit FPU registers. Signed-off-by: Keith Packard <keithp@keithp.com> [Palmer: This requires manually triggering a rebuild of riscv32-softmmu/gdbstub-xml.c] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-02-10 12:01:36 -08:00
..
insn_trans	target/riscv: fsd/fsw doesn't dirty FP state	2020-01-16 10:03:08 -08:00
cpu_bits.h
cpu_helper.c	tcg: Search includes from the project root source directory	2020-01-15 15:13:10 -10:00
cpu_user.h
cpu-param.h
cpu.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
cpu.h	target/riscv: Fix tb->flags FS status	2020-01-16 10:02:58 -08:00
csr.c	target/riscv: update mstatus.SD when FS is set dirty	2020-01-16 10:03:15 -08:00
fpu_helper.c
gdbstub.c	riscv: Separate FPU register size from core register size in gdbstub [v2]	2020-02-10 12:01:36 -08:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
Makefile.objs
monitor.c
op_helper.c	riscv: Set xPIE to 1 after xRET	2020-01-16 10:02:41 -08:00
pmp.c	target/riscv: PMP violation due to wrong size parameter	2019-10-28 08:46:33 -07:00
pmp.h
trace-events
translate.c	RISC-V Patches for the 5.0 Soft Freeze, Part 1	2020-01-24 12:34:04 +00:00