ca6155c0f2
This series removes ad hoc RAM allocation API (memory_region_allocate_system_memory) and consolidates it around hostmem backend. It allows to * resolve conflicts between global -mem-prealloc and hostmem's "policy" option, fixing premature allocation before binding policy is applied * simplify complicated memory allocation routines which had to deal with 2 ways to allocate RAM. * reuse hostmem backends of a choice for main RAM without adding extra CLI options to duplicate hostmem features. A recent case was -mem-shared, to enable vhost-user on targets that don't support hostmem backends [1] (ex: s390) * move RAM allocation from individual boards into generic machine code and provide them with prepared MemoryRegion. * clean up deprecated NUMA features which were tied to the old API (see patches) - "numa: remove deprecated -mem-path fallback to anonymous RAM" - (POSTPONED, waiting on libvirt side) "forbid '-numa node,mem' for 5.0 and newer machine types" - (POSTPONED) "numa: remove deprecated implicit RAM distribution between nodes" Introduce a new machine.memory-backend property and wrapper code that aliases global -mem-path and -mem-alloc into automatically created hostmem backend properties (provided memory-backend was not set explicitly given by user). A bulk of trivial patches then follow to incrementally convert individual boards to using machine.memory-backend provided MemoryRegion. Board conversion typically involves: * providing MachineClass::default_ram_size and MachineClass::default_ram_id so generic code could create default backend if user didn't explicitly provide memory-backend or -m options * dropping memory_region_allocate_system_memory() call * using convenience MachineState::ram MemoryRegion, which points to MemoryRegion allocated by ram-memdev On top of that for some boards: * missing ram_size checks are added (typically it were boards with fixed ram size) * ram_size fixups are replaced by checks and hard errors, forcing user to provide correct "-m" values instead of ignoring it and continuing running. After all boards are converted, the old API is removed and memory allocation routines are cleaned up.
490 lines
17 KiB
C
490 lines
17 KiB
C
/*
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* Xilinx Versal Virtual board.
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*
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* Copyright (c) 2018 Xilinx Inc.
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* Written by Edgar E. Iglesias
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/arm/sysbus-fdt.h"
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#include "hw/arm/fdt.h"
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#include "cpu.h"
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#include "hw/arm/xlnx-versal.h"
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#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
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#define XLNX_VERSAL_VIRT_MACHINE(obj) \
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OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
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typedef struct VersalVirt {
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MachineState parent_obj;
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Versal soc;
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void *fdt;
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int fdt_size;
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struct {
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uint32_t gic;
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uint32_t ethernet_phy[2];
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uint32_t clk_125Mhz;
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uint32_t clk_25Mhz;
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} phandle;
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struct arm_boot_info binfo;
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struct {
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bool secure;
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} cfg;
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} VersalVirt;
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static void fdt_create(VersalVirt *s)
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{
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MachineClass *mc = MACHINE_GET_CLASS(s);
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int i;
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s->fdt = create_device_tree(&s->fdt_size);
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if (!s->fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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/* Allocate all phandles. */
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s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
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for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
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s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
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}
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s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
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s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
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/* Create /chosen node for load_dtb. */
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qemu_fdt_add_subnode(s->fdt, "/chosen");
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/* Header */
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qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
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qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
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qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
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}
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static void fdt_add_clk_node(VersalVirt *s, const char *name,
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unsigned int freq_hz, uint32_t phandle)
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{
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
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qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
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qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
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qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
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qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
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}
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static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
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{
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int i;
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qemu_fdt_add_subnode(s->fdt, "/cpus");
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qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
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for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
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char *name = g_strdup_printf("/cpus/cpu@%d", i);
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ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
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if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
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qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
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}
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qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
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qemu_fdt_setprop_string(s->fdt, name, "compatible",
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armcpu->dtb_compatible);
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g_free(name);
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}
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}
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static void fdt_add_gic_nodes(VersalVirt *s)
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{
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char *nodename;
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nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
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qemu_fdt_add_subnode(s->fdt, nodename);
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qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
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qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
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2, MM_GIC_APU_DIST_MAIN,
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2, MM_GIC_APU_DIST_MAIN_SIZE,
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2, MM_GIC_APU_REDIST_0,
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2, MM_GIC_APU_REDIST_0_SIZE);
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qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
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qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
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g_free(nodename);
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}
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static void fdt_add_timer_nodes(VersalVirt *s)
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{
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const char compat[] = "arm,armv8-timer";
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uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
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qemu_fdt_add_subnode(s->fdt, "/timer");
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qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
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GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
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qemu_fdt_setprop(s->fdt, "/timer", "compatible",
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compat, sizeof(compat));
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}
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static void fdt_add_uart_nodes(VersalVirt *s)
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{
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uint64_t addrs[] = { MM_UART1, MM_UART0 };
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unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
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const char compat[] = "arm,pl011\0arm,sbsa-uart";
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const char clocknames[] = "uartclk\0apb_pclk";
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int i;
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for (i = 0; i < ARRAY_SIZE(addrs); i++) {
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char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addrs[i], 2, 0x1000);
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qemu_fdt_setprop(s->fdt, name, "compatible",
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compat, sizeof(compat));
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qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
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if (addrs[i] == MM_UART0) {
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/* Select UART0. */
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qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
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}
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g_free(name);
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}
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}
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static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
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uint32_t phandle)
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{
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char *name = g_strdup_printf("%s/fixed-link", gemname);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
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qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
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qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
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g_free(name);
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}
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static void fdt_add_gem_nodes(VersalVirt *s)
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{
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uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
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unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
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const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
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const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
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int i;
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for (i = 0; i < ARRAY_SIZE(addrs); i++) {
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char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
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qemu_fdt_add_subnode(s->fdt, name);
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fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
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qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
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qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
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s->phandle.ethernet_phy[i]);
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qemu_fdt_setprop_cells(s->fdt, name, "clocks",
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
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s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
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qemu_fdt_setprop(s->fdt, name, "clock-names",
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clocknames, sizeof(clocknames));
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI,
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GIC_FDT_IRQ_TYPE_SPI, irqs[i],
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GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, addrs[i], 2, 0x1000);
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qemu_fdt_setprop(s->fdt, name, "compatible",
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compat_gem, sizeof(compat_gem));
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qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
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qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
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g_free(name);
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}
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}
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static void fdt_nop_memory_nodes(void *fdt, Error **errp)
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{
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Error *err = NULL;
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char **node_path;
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int n = 0;
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node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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while (node_path[n]) {
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if (g_str_has_prefix(node_path[n], "/memory")) {
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qemu_fdt_nop_node(fdt, node_path[n]);
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}
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n++;
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}
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g_strfreev(node_path);
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}
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static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
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{
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/* Describes the various split DDR access regions. */
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static const struct {
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uint64_t base;
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uint64_t size;
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} addr_ranges[] = {
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{ MM_TOP_DDR, MM_TOP_DDR_SIZE },
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{ MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
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{ MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
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{ MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
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};
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uint64_t mem_reg_prop[8] = {0};
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uint64_t size = ram_size;
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Error *err = NULL;
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char *name;
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int i;
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fdt_nop_memory_nodes(fdt, &err);
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if (err) {
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error_report_err(err);
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return;
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}
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name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
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for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
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uint64_t mapsize;
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mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
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mem_reg_prop[i * 2] = addr_ranges[i].base;
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mem_reg_prop[i * 2 + 1] = mapsize;
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size -= mapsize;
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}
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qemu_fdt_add_subnode(fdt, name);
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qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
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switch (i) {
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case 1:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1]);
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break;
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case 2:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3]);
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break;
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case 3:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3],
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2, mem_reg_prop[4],
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2, mem_reg_prop[5]);
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break;
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case 4:
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qemu_fdt_setprop_sized_cells(fdt, name, "reg",
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2, mem_reg_prop[0],
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2, mem_reg_prop[1],
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2, mem_reg_prop[2],
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2, mem_reg_prop[3],
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2, mem_reg_prop[4],
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2, mem_reg_prop[5],
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2, mem_reg_prop[6],
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2, mem_reg_prop[7]);
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break;
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default:
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g_assert_not_reached();
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}
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g_free(name);
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}
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static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
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void *fdt)
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{
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VersalVirt *s = container_of(binfo, VersalVirt, binfo);
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fdt_add_memory_nodes(s, fdt, binfo->ram_size);
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}
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static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
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int *fdt_size)
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{
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const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
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*fdt_size = board->fdt_size;
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return board->fdt;
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}
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#define NUM_VIRTIO_TRANSPORT 8
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static void create_virtio_regions(VersalVirt *s)
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{
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int virtio_mmio_size = 0x200;
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int i;
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for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
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char *name = g_strdup_printf("virtio%d", i);
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hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
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int irq = VERSAL_RSVD_IRQ_FIRST + i;
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MemoryRegion *mr;
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DeviceState *dev;
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qemu_irq pic_irq;
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pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
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dev = qdev_create(NULL, "virtio-mmio");
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object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
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&error_fatal);
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qdev_init_nofail(dev);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
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mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_add_subregion(&s->soc.mr_ps, base, mr);
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g_free(name);
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}
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for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
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hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
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int irq = VERSAL_RSVD_IRQ_FIRST + i;
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char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
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qemu_fdt_add_subnode(s->fdt, name);
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qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
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GIC_FDT_IRQ_TYPE_SPI, irq,
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GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
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qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
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2, base, 2, virtio_mmio_size);
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qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
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g_free(name);
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}
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}
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static void versal_virt_init(MachineState *machine)
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{
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VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
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int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
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/*
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* If the user provides an Operating System to be loaded, we expect them
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* to use the -kernel command line option.
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*
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* Users can load firmware or boot-loaders with the -device loader options.
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*
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* When loading an OS, we generate a dtb and let arm_load_kernel() select
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* where it gets loaded. This dtb will be passed to the kernel in x0.
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*
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* If there's no -kernel option, we generate a DTB and place it at 0x1000
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* for the bootloaders or firmware to pick up.
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*
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* If users want to provide their own DTB, they can use the -dtb option.
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* These dtb's will have their memory nodes modified to match QEMU's
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* selected ram_size option before they get passed to the kernel or fw.
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*
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* When loading an OS, we turn on QEMU's PSCI implementation with SMC
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* as the PSCI conduit. When there's no -kernel, we assume the user
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* provides EL3 firmware to handle PSCI.
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*/
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if (machine->kernel_filename) {
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psci_conduit = QEMU_PSCI_CONDUIT_SMC;
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}
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sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
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sizeof(s->soc), TYPE_XLNX_VERSAL);
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object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
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"ddr", &error_abort);
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object_property_set_int(OBJECT(&s->soc), psci_conduit,
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"psci-conduit", &error_abort);
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object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
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fdt_create(s);
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create_virtio_regions(s);
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fdt_add_gem_nodes(s);
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fdt_add_uart_nodes(s);
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fdt_add_gic_nodes(s);
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fdt_add_timer_nodes(s);
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fdt_add_cpu_nodes(s, psci_conduit);
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fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
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fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
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/* Make the APU cpu address space visible to virtio and other
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* modules unaware of muliple address-spaces. */
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memory_region_add_subregion_overlap(get_system_memory(),
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0, &s->soc.fpd.apu.mr, 0);
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s->binfo.ram_size = machine->ram_size;
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s->binfo.loader_start = 0x0;
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s->binfo.get_dtb = versal_virt_get_dtb;
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s->binfo.modify_dtb = versal_virt_modify_dtb;
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if (machine->kernel_filename) {
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arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
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} else {
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AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
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&s->binfo);
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/* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
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* Offset things by 4K. */
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s->binfo.loader_start = 0x1000;
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s->binfo.dtb_limit = 0x1000000;
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if (arm_load_dtb(s->binfo.loader_start,
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&s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
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exit(EXIT_FAILURE);
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}
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}
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}
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static void versal_virt_machine_instance_init(Object *obj)
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{
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}
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static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Xilinx Versal Virtual development board";
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mc->init = versal_virt_init;
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mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
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mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
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mc->no_cdrom = true;
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mc->default_ram_id = "ddr";
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}
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static const TypeInfo versal_virt_machine_init_typeinfo = {
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.name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
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.parent = TYPE_MACHINE,
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.class_init = versal_virt_machine_class_init,
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.instance_init = versal_virt_machine_instance_init,
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.instance_size = sizeof(VersalVirt),
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};
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static void versal_virt_machine_init_register_types(void)
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{
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type_register_static(&versal_virt_machine_init_typeinfo);
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}
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type_init(versal_virt_machine_init_register_types)
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