2efc6be2ea
Commitsf606604f1c
,2c17449b30
and5ce5944dc0
added usages of ENV_GET_CPU() macro in target-specific code. Use s390_env_get_cpu() instead. Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
813 lines
22 KiB
C
813 lines
22 KiB
C
/*
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* S/390 helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/timer.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#endif
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//#define DEBUG_S390
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//#define DEBUG_S390_PTE
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//#define DEBUG_S390_STDOUT
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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qemu_log(fmt, ##__VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifdef DEBUG_S390_PTE
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#define PTE_DPRINTF DPRINTF
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#else
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#define PTE_DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifndef CONFIG_USER_ONLY
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void s390x_tod_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_TOD;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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void s390x_cpu_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_CPUTIMER;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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#endif
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S390CPU *cpu_s390x_init(const char *cpu_model)
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{
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S390CPU *cpu;
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cpu = S390_CPU(object_new(TYPE_S390_CPU));
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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#if defined(CONFIG_USER_ONLY)
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void s390_cpu_do_interrupt(CPUState *cs)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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env->exception_index = -1;
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}
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int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
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int rw, int mmu_idx)
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{
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env->exception_index = EXCP_PGM;
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env->int_pgm_code = PGM_ADDRESSING;
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/* On real machines this value is dropped into LowMem. Since this
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is userland, simply put this someplace that cpu_loop can find it. */
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env->__excp_addr = address;
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return 1;
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}
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#else /* !CONFIG_USER_ONLY */
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/* Ensure to exit the TB after this call! */
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static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
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uint32_t ilen)
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{
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env->exception_index = EXCP_PGM;
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env->int_pgm_code = code;
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env->int_pgm_ilen = ilen;
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}
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static int trans_bits(CPUS390XState *env, uint64_t mode)
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{
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int bits = 0;
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switch (mode) {
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case PSW_ASC_PRIMARY:
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bits = 1;
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break;
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case PSW_ASC_SECONDARY:
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bits = 2;
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break;
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case PSW_ASC_HOME:
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bits = 3;
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break;
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default:
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cpu_abort(env, "unknown asc mode\n");
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break;
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}
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return bits;
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}
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static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
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uint64_t mode)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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int ilen = ILEN_LATER_INC;
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int bits = trans_bits(env, mode) | 4;
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DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
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stq_phys(cs->as,
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env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
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trigger_pgm_exception(env, PGM_PROTECTION, ilen);
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}
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static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
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uint32_t type, uint64_t asc, int rw)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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int ilen = ILEN_LATER;
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int bits = trans_bits(env, asc);
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/* Code accesses have an undefined ilc. */
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if (rw == 2) {
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ilen = 2;
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}
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DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
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stq_phys(cs->as,
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env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
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trigger_pgm_exception(env, type, ilen);
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}
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static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, int level,
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target_ulong *raddr, int *flags, int rw)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint64_t offs = 0;
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uint64_t origin;
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uint64_t new_asce;
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PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
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if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
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((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
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/* XXX different regions have different faults */
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DPRINTF("%s: invalid region\n", __func__);
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trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
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return -1;
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}
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if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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if (asce & _ASCE_REAL_SPACE) {
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/* direct mapping */
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*raddr = vaddr;
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return 0;
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}
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origin = asce & _ASCE_ORIGIN;
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switch (level) {
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case _ASCE_TYPE_REGION1 + 4:
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offs = (vaddr >> 50) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION1:
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offs = (vaddr >> 39) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION2:
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offs = (vaddr >> 28) & 0x3ff8;
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break;
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case _ASCE_TYPE_REGION3:
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offs = (vaddr >> 17) & 0x3ff8;
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break;
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case _ASCE_TYPE_SEGMENT:
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offs = (vaddr >> 9) & 0x07f8;
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origin = asce & _SEGMENT_ENTRY_ORIGIN;
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break;
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}
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/* XXX region protection flags */
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/* *flags &= ~PAGE_WRITE */
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new_asce = ldq_phys(cs->as, origin + offs);
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PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
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__func__, origin, offs, new_asce);
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if (level != _ASCE_TYPE_SEGMENT) {
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/* yet another region */
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return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
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flags, rw);
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}
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/* PTE */
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if (new_asce & _PAGE_INVALID) {
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DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
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trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
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return -1;
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}
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if (new_asce & _PAGE_RO) {
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*flags &= ~PAGE_WRITE;
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}
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*raddr = new_asce & _ASCE_ORIGIN;
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PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
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return 0;
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}
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static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, target_ulong *raddr, int *flags,
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int rw)
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{
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uint64_t asce = 0;
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int level, new_level;
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int r;
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switch (asc) {
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case PSW_ASC_PRIMARY:
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PTE_DPRINTF("%s: asc=primary\n", __func__);
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asce = env->cregs[1];
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break;
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case PSW_ASC_SECONDARY:
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PTE_DPRINTF("%s: asc=secondary\n", __func__);
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asce = env->cregs[7];
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break;
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case PSW_ASC_HOME:
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PTE_DPRINTF("%s: asc=home\n", __func__);
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asce = env->cregs[13];
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break;
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}
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switch (asce & _ASCE_TYPE_MASK) {
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case _ASCE_TYPE_REGION1:
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break;
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case _ASCE_TYPE_REGION2:
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if (vaddr & 0xffe0000000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffe0000000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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case _ASCE_TYPE_REGION3:
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if (vaddr & 0xfffffc0000000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xfffffc0000000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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case _ASCE_TYPE_SEGMENT:
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if (vaddr & 0xffffffff80000000ULL) {
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DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
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" 0xffffffff80000000ULL\n", __func__, vaddr);
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trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
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return -1;
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}
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break;
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}
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/* fake level above current */
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level = asce & _ASCE_TYPE_MASK;
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new_level = level + 4;
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asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
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r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
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if ((rw == 1) && !(*flags & PAGE_WRITE)) {
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trigger_prot_fault(env, vaddr, asc);
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return -1;
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}
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return r;
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}
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags)
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{
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int r = -1;
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uint8_t *sk;
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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vaddr &= TARGET_PAGE_MASK;
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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*raddr = vaddr;
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r = 0;
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goto out;
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}
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switch (asc) {
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case PSW_ASC_PRIMARY:
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case PSW_ASC_HOME:
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r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
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break;
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case PSW_ASC_SECONDARY:
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/*
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* Instruction: Primary
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* Data: Secondary
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*/
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if (rw == 2) {
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r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
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rw);
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*flags &= ~(PAGE_READ | PAGE_WRITE);
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} else {
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r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
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rw);
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*flags &= ~(PAGE_EXEC);
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}
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break;
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case PSW_ASC_ACCREG:
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default:
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hw_error("guest switched to unknown asc mode\n");
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break;
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}
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out:
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/* Convert real address -> absolute address */
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if (*raddr < 0x2000) {
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*raddr = *raddr + env->psa;
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}
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if (*raddr <= ram_size) {
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sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
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if (*flags & PAGE_READ) {
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*sk |= SK_R;
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}
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if (*flags & PAGE_WRITE) {
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*sk |= SK_C;
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}
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}
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return r;
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}
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int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
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int rw, int mmu_idx)
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{
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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target_ulong vaddr, raddr;
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int prot;
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DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
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__func__, orig_vaddr, rw, mmu_idx);
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orig_vaddr &= TARGET_PAGE_MASK;
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vaddr = orig_vaddr;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
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/* Translation ended in exception */
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return 1;
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}
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/* check out of RAM access */
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if (raddr > (ram_size + virtio_size)) {
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DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
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(uint64_t)raddr, (uint64_t)ram_size);
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trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
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return 1;
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}
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DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
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(uint64_t)vaddr, (uint64_t)raddr, prot);
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tlb_set_page(env, orig_vaddr, raddr, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong raddr;
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int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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int old_exc = env->exception_index;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
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env->exception_index = old_exc;
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return raddr;
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}
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void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
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{
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if (mask & PSW_MASK_WAIT) {
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S390CPU *cpu = s390_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
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if (s390_del_running_cpu(cpu) == 0) {
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#ifndef CONFIG_USER_ONLY
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qemu_system_shutdown_request();
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#endif
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}
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}
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cs->halted = 1;
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env->exception_index = EXCP_HLT;
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}
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env->psw.addr = addr;
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env->psw.mask = mask;
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env->cc_op = (mask >> 44) & 3;
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}
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static uint64_t get_psw_mask(CPUS390XState *env)
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{
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uint64_t r;
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env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
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r = env->psw.mask;
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r &= ~PSW_MASK_CC;
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assert(!(env->cc_op & ~3));
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r |= (uint64_t)env->cc_op << 44;
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return r;
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}
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static LowCore *cpu_map_lowcore(CPUS390XState *env)
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{
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LowCore *lowcore;
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hwaddr len = sizeof(LowCore);
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lowcore = cpu_physical_memory_map(env->psa, &len, 1);
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if (len < sizeof(LowCore)) {
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cpu_abort(env, "Could not map lowcore\n");
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}
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return lowcore;
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}
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static void cpu_unmap_lowcore(LowCore *lowcore)
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{
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cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
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}
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void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
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int is_write)
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{
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hwaddr start = addr;
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/* Mind the prefix area. */
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if (addr < 8192) {
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/* Map the lowcore. */
|
|
start += env->psa;
|
|
*len = MIN(*len, 8192 - addr);
|
|
} else if ((addr >= env->psa) && (addr < env->psa + 8192)) {
|
|
/* Map the 0 page. */
|
|
start -= env->psa;
|
|
*len = MIN(*len, 8192 - start);
|
|
}
|
|
|
|
return cpu_physical_memory_map(start, len, is_write);
|
|
}
|
|
|
|
void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
|
|
int is_write)
|
|
{
|
|
cpu_physical_memory_unmap(addr, len, is_write, len);
|
|
}
|
|
|
|
static void do_svc_interrupt(CPUS390XState *env)
|
|
{
|
|
uint64_t mask, addr;
|
|
LowCore *lowcore;
|
|
|
|
lowcore = cpu_map_lowcore(env);
|
|
|
|
lowcore->svc_code = cpu_to_be16(env->int_svc_code);
|
|
lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
|
|
lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
|
|
mask = be64_to_cpu(lowcore->svc_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->svc_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
static void do_program_interrupt(CPUS390XState *env)
|
|
{
|
|
uint64_t mask, addr;
|
|
LowCore *lowcore;
|
|
int ilen = env->int_pgm_ilen;
|
|
|
|
switch (ilen) {
|
|
case ILEN_LATER:
|
|
ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
|
|
break;
|
|
case ILEN_LATER_INC:
|
|
ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
|
|
env->psw.addr += ilen;
|
|
break;
|
|
default:
|
|
assert(ilen == 2 || ilen == 4 || ilen == 6);
|
|
}
|
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
|
|
__func__, env->int_pgm_code, ilen);
|
|
|
|
lowcore = cpu_map_lowcore(env);
|
|
|
|
lowcore->pgm_ilen = cpu_to_be16(ilen);
|
|
lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
|
|
lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
mask = be64_to_cpu(lowcore->program_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->program_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
|
|
env->int_pgm_code, ilen, env->psw.mask,
|
|
env->psw.addr);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
#define VIRTIO_SUBCODE_64 0x0D00
|
|
|
|
static void do_ext_interrupt(CPUS390XState *env)
|
|
{
|
|
uint64_t mask, addr;
|
|
LowCore *lowcore;
|
|
ExtQueue *q;
|
|
|
|
if (!(env->psw.mask & PSW_MASK_EXT)) {
|
|
cpu_abort(env, "Ext int w/o ext mask\n");
|
|
}
|
|
|
|
if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
|
|
cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
|
|
}
|
|
|
|
q = &env->ext_queue[env->ext_index];
|
|
lowcore = cpu_map_lowcore(env);
|
|
|
|
lowcore->ext_int_code = cpu_to_be16(q->code);
|
|
lowcore->ext_params = cpu_to_be32(q->param);
|
|
lowcore->ext_params2 = cpu_to_be64(q->param64);
|
|
lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
|
|
mask = be64_to_cpu(lowcore->external_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->external_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
env->ext_index--;
|
|
if (env->ext_index == -1) {
|
|
env->pending_int &= ~INTERRUPT_EXT;
|
|
}
|
|
|
|
DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
|
|
env->psw.mask, env->psw.addr);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
static void do_io_interrupt(CPUS390XState *env)
|
|
{
|
|
LowCore *lowcore;
|
|
IOIntQueue *q;
|
|
uint8_t isc;
|
|
int disable = 1;
|
|
int found = 0;
|
|
|
|
if (!(env->psw.mask & PSW_MASK_IO)) {
|
|
cpu_abort(env, "I/O int w/o I/O mask\n");
|
|
}
|
|
|
|
for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
|
|
uint64_t isc_bits;
|
|
|
|
if (env->io_index[isc] < 0) {
|
|
continue;
|
|
}
|
|
if (env->io_index[isc] > MAX_IO_QUEUE) {
|
|
cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
|
|
isc, env->io_index[isc]);
|
|
}
|
|
|
|
q = &env->io_queue[env->io_index[isc]][isc];
|
|
isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
|
|
if (!(env->cregs[6] & isc_bits)) {
|
|
disable = 0;
|
|
continue;
|
|
}
|
|
if (!found) {
|
|
uint64_t mask, addr;
|
|
|
|
found = 1;
|
|
lowcore = cpu_map_lowcore(env);
|
|
|
|
lowcore->subchannel_id = cpu_to_be16(q->id);
|
|
lowcore->subchannel_nr = cpu_to_be16(q->nr);
|
|
lowcore->io_int_parm = cpu_to_be32(q->parm);
|
|
lowcore->io_int_word = cpu_to_be32(q->word);
|
|
lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
mask = be64_to_cpu(lowcore->io_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->io_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
env->io_index[isc]--;
|
|
|
|
DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
|
|
env->psw.mask, env->psw.addr);
|
|
load_psw(env, mask, addr);
|
|
}
|
|
if (env->io_index[isc] >= 0) {
|
|
disable = 0;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
if (disable) {
|
|
env->pending_int &= ~INTERRUPT_IO;
|
|
}
|
|
|
|
}
|
|
|
|
static void do_mchk_interrupt(CPUS390XState *env)
|
|
{
|
|
uint64_t mask, addr;
|
|
LowCore *lowcore;
|
|
MchkQueue *q;
|
|
int i;
|
|
|
|
if (!(env->psw.mask & PSW_MASK_MCHECK)) {
|
|
cpu_abort(env, "Machine check w/o mchk mask\n");
|
|
}
|
|
|
|
if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
|
|
cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
|
|
}
|
|
|
|
q = &env->mchk_queue[env->mchk_index];
|
|
|
|
if (q->type != 1) {
|
|
/* Don't know how to handle this... */
|
|
cpu_abort(env, "Unknown machine check type %d\n", q->type);
|
|
}
|
|
if (!(env->cregs[14] & (1 << 28))) {
|
|
/* CRW machine checks disabled */
|
|
return;
|
|
}
|
|
|
|
lowcore = cpu_map_lowcore(env);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll);
|
|
lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
|
|
lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
|
|
lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
|
|
}
|
|
lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
|
|
lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
|
|
lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
|
|
lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
|
|
lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
|
|
lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
|
|
lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
|
|
|
|
lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
|
|
lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
|
|
lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
|
|
lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
env->mchk_index--;
|
|
if (env->mchk_index == -1) {
|
|
env->pending_int &= ~INTERRUPT_MCHK;
|
|
}
|
|
|
|
DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
|
|
env->psw.mask, env->psw.addr);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
void s390_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
|
|
__func__, env->exception_index, env->psw.addr);
|
|
|
|
s390_add_running_cpu(cpu);
|
|
/* handle machine checks */
|
|
if ((env->psw.mask & PSW_MASK_MCHECK) &&
|
|
(env->exception_index == -1)) {
|
|
if (env->pending_int & INTERRUPT_MCHK) {
|
|
env->exception_index = EXCP_MCHK;
|
|
}
|
|
}
|
|
/* handle external interrupts */
|
|
if ((env->psw.mask & PSW_MASK_EXT) &&
|
|
env->exception_index == -1) {
|
|
if (env->pending_int & INTERRUPT_EXT) {
|
|
/* code is already in env */
|
|
env->exception_index = EXCP_EXT;
|
|
} else if (env->pending_int & INTERRUPT_TOD) {
|
|
cpu_inject_ext(cpu, 0x1004, 0, 0);
|
|
env->exception_index = EXCP_EXT;
|
|
env->pending_int &= ~INTERRUPT_EXT;
|
|
env->pending_int &= ~INTERRUPT_TOD;
|
|
} else if (env->pending_int & INTERRUPT_CPUTIMER) {
|
|
cpu_inject_ext(cpu, 0x1005, 0, 0);
|
|
env->exception_index = EXCP_EXT;
|
|
env->pending_int &= ~INTERRUPT_EXT;
|
|
env->pending_int &= ~INTERRUPT_TOD;
|
|
}
|
|
}
|
|
/* handle I/O interrupts */
|
|
if ((env->psw.mask & PSW_MASK_IO) &&
|
|
(env->exception_index == -1)) {
|
|
if (env->pending_int & INTERRUPT_IO) {
|
|
env->exception_index = EXCP_IO;
|
|
}
|
|
}
|
|
|
|
switch (env->exception_index) {
|
|
case EXCP_PGM:
|
|
do_program_interrupt(env);
|
|
break;
|
|
case EXCP_SVC:
|
|
do_svc_interrupt(env);
|
|
break;
|
|
case EXCP_EXT:
|
|
do_ext_interrupt(env);
|
|
break;
|
|
case EXCP_IO:
|
|
do_io_interrupt(env);
|
|
break;
|
|
case EXCP_MCHK:
|
|
do_mchk_interrupt(env);
|
|
break;
|
|
}
|
|
env->exception_index = -1;
|
|
|
|
if (!env->pending_int) {
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_USER_ONLY */
|