409 lines
13 KiB
C
409 lines
13 KiB
C
/*
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* QEMU PREP PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2011-2013 Andreas Färber
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "hw/i386/pc.h"
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#include "hw/loader.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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#define TYPE_RAVEN_PCI_DEVICE "raven"
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#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
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#define RAVEN_PCI_DEVICE(obj) \
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OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
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typedef struct RavenPCIState {
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PCIDevice dev;
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uint32_t elf_machine;
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char *bios_name;
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MemoryRegion bios;
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} RavenPCIState;
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#define RAVEN_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
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typedef struct PRePPCIState {
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PCIHostState parent_obj;
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qemu_irq irq[PCI_NUM_PINS];
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PCIBus pci_bus;
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AddressSpace pci_io_as;
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MemoryRegion pci_io;
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MemoryRegion pci_io_non_contiguous;
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MemoryRegion pci_memory;
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MemoryRegion pci_intack;
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MemoryRegion bm;
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MemoryRegion bm_ram_alias;
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MemoryRegion bm_pci_memory_alias;
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AddressSpace bm_as;
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RavenPCIState pci_dev;
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int contiguous_map;
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} PREPPCIState;
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#define BIOS_SIZE (1024 * 1024)
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static inline uint32_t raven_pci_io_config(hwaddr addr)
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{
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int i;
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for (i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0) {
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break;
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}
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}
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return (addr & 0x7ff) | (i << 11);
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}
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static void raven_pci_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
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}
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static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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PCIHostState *phb = PCI_HOST_BRIDGE(s);
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return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
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}
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static const MemoryRegionOps raven_pci_io_ops = {
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.read = raven_pci_io_read,
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.write = raven_pci_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t raven_intack_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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return pic_read_irq(isa_pic);
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}
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static const MemoryRegionOps raven_intack_ops = {
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.read = raven_intack_read,
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.valid = {
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.max_access_size = 1,
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},
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};
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static inline hwaddr raven_io_address(PREPPCIState *s,
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hwaddr addr)
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{
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if (s->contiguous_map == 0) {
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
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}
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/* FIXME: handle endianness switch */
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return addr;
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}
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static uint64_t raven_io_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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address_space_read(&s->pci_io_as, addr + 0x80000000,
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MEMTXATTRS_UNSPECIFIED, buf, size);
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if (size == 1) {
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return buf[0];
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} else if (size == 2) {
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return lduw_le_p(buf);
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} else if (size == 4) {
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return ldl_le_p(buf);
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} else {
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g_assert_not_reached();
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}
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}
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static void raven_io_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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uint8_t buf[4];
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addr = raven_io_address(s, addr);
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if (size == 1) {
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buf[0] = val;
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} else if (size == 2) {
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stw_le_p(buf, val);
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} else if (size == 4) {
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stl_le_p(buf, val);
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} else {
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g_assert_not_reached();
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}
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address_space_write(&s->pci_io_as, addr + 0x80000000,
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MEMTXATTRS_UNSPECIFIED, buf, size);
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}
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static const MemoryRegionOps raven_io_ops = {
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.read = raven_io_read,
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.write = raven_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.max_access_size = 4,
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.valid.unaligned = true,
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};
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static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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}
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static void raven_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num] , level);
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}
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static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
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int devfn)
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{
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PREPPCIState *s = opaque;
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return &s->bm_as;
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}
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static void raven_change_gpio(void *opaque, int n, int level)
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{
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PREPPCIState *s = opaque;
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s->contiguous_map = level;
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}
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static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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PCIHostState *h = PCI_HOST_BRIDGE(dev);
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
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MemoryRegion *address_space_mem = get_system_memory();
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int i;
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for (i = 0; i < PCI_NUM_PINS; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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qdev_init_gpio_in(d, raven_change_gpio, 1);
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pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
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PCI_NUM_PINS);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4);
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memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
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"pci-conf-data", 4);
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memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
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memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
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"pciio", 0x00400000);
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memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
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memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
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"pci-intack", 1);
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
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/* TODO Remove once realize propagates to child devices. */
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object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
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object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
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}
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static void raven_pcihost_initfn(Object *obj)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
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MemoryRegion *address_space_mem = get_system_memory();
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DeviceState *pci_dev;
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memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
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memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
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"pci-io-non-contiguous", 0x00800000);
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memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
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address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
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/* CPU address space */
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memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
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memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
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&s->pci_io_non_contiguous, 1);
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memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
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pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
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&s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
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/* Bus master address space */
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memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
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memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
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&s->pci_memory, 0,
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memory_region_size(&s->pci_memory));
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memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
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get_system_memory(), 0, 0x80000000);
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memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
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memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
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address_space_init(&s->bm_as, &s->bm, "raven-bm");
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pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
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h->bus = &s->pci_bus;
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object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
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pci_dev = DEVICE(&s->pci_dev);
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qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
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object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
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NULL);
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qdev_prop_set_bit(pci_dev, "multifunction", false);
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}
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static void raven_realize(PCIDevice *d, Error **errp)
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{
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RavenPCIState *s = RAVEN_PCI_DEVICE(d);
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char *filename;
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int bios_size = -1;
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
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&error_fatal);
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memory_region_set_readonly(&s->bios, true);
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memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
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&s->bios);
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if (s->bios_name) {
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
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if (filename) {
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if (s->elf_machine != EM_NONE) {
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bios_size = load_elf(filename, NULL, NULL, NULL,
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NULL, NULL, 1, s->elf_machine, 0, 0);
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}
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if (bios_size < 0) {
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bios_size = get_image_size(filename);
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if (bios_size > 0 && bios_size <= BIOS_SIZE) {
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hwaddr bios_addr;
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bios_size = (bios_size + 0xfff) & ~0xfff;
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bios_addr = (uint32_t)(-BIOS_SIZE);
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bios_size = load_image_targphys(filename, bios_addr,
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bios_size);
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}
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}
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}
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g_free(filename);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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memory_region_del_subregion(get_system_memory(), &s->bios);
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error_setg(errp, "Could not load bios image '%s'", s->bios_name);
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return;
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}
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}
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vmstate_register_ram_global(&s->bios);
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}
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static const VMStateDescription vmstate_raven = {
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.name = "raven",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, RavenPCIState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void raven_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = raven_realize;
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k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
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k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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dc->desc = "PReP Host Bridge - Motorola Raven";
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dc->vmsd = &vmstate_raven;
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/*
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* Reason: PCI-facing part of the host bridge, not usable without
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* the host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo raven_info = {
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.name = TYPE_RAVEN_PCI_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(RavenPCIState),
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.class_init = raven_class_init,
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};
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static Property raven_pcihost_properties[] = {
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DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
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EM_NONE),
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DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
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DEFINE_PROP_END_OF_LIST()
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};
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static void raven_pcihost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->realize = raven_pcihost_realizefn;
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dc->props = raven_pcihost_properties;
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dc->fw_name = "pci";
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}
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static const TypeInfo raven_pcihost_info = {
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.name = TYPE_RAVEN_PCI_HOST_BRIDGE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(PREPPCIState),
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.instance_init = raven_pcihost_initfn,
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.class_init = raven_pcihost_class_init,
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};
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static void raven_register_types(void)
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{
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type_register_static(&raven_pcihost_info);
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type_register_static(&raven_info);
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}
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type_init(raven_register_types)
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