663 lines
19 KiB
C
663 lines
19 KiB
C
/*
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* MSI-X device support
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*
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* This module includes support for MSI-X in pci devices.
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/pci.h"
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#include "hw/xen/xen.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "trace.h"
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#define MSIX_CAP_LENGTH 12
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/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
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#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
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MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
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{
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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MSIMessage msg;
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msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
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msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
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return msg;
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}
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/*
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* Special API for POWER to configure the vectors through
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* a side channel. Should never be used by devices.
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*/
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void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg)
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{
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address);
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pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data);
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table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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static uint8_t msix_pending_mask(int vector)
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{
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return 1 << (vector % 8);
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}
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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return dev->msix_pba + vector / 8;
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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{
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return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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}
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void msix_set_pending(PCIDevice *dev, unsigned int vector)
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{
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*msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
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}
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void msix_clr_pending(PCIDevice *dev, int vector)
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{
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*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
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}
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static bool msix_vector_masked(PCIDevice *dev, unsigned int vector, bool fmask)
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{
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unsigned offset = vector * PCI_MSIX_ENTRY_SIZE;
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uint8_t *data = &dev->msix_table[offset + PCI_MSIX_ENTRY_DATA];
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/* MSIs on Xen can be remapped into pirqs. In those cases, masking
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* and unmasking go through the PV evtchn path. */
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if (xen_enabled() && xen_is_pirq_msi(pci_get_long(data))) {
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return false;
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}
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return fmask || dev->msix_table[offset + PCI_MSIX_ENTRY_VECTOR_CTRL] &
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PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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bool msix_is_masked(PCIDevice *dev, unsigned int vector)
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{
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return msix_vector_masked(dev, vector, dev->msix_function_masked);
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}
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static void msix_fire_vector_notifier(PCIDevice *dev,
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unsigned int vector, bool is_masked)
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{
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MSIMessage msg;
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int ret;
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if (!dev->msix_vector_use_notifier) {
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return;
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}
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if (is_masked) {
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dev->msix_vector_release_notifier(dev, vector);
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} else {
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msg = msix_get_message(dev, vector);
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ret = dev->msix_vector_use_notifier(dev, vector, msg);
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assert(ret >= 0);
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}
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}
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static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
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{
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bool is_masked = msix_is_masked(dev, vector);
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if (is_masked == was_masked) {
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return;
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}
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msix_fire_vector_notifier(dev, vector, is_masked);
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if (!is_masked && msix_is_pending(dev, vector)) {
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msix_clr_pending(dev, vector);
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msix_notify(dev, vector);
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}
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}
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static bool msix_masked(PCIDevice *dev)
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{
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return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
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}
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static void msix_update_function_masked(PCIDevice *dev)
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{
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dev->msix_function_masked = !msix_enabled(dev) || msix_masked(dev);
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}
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/* Handle MSI-X capability config write. */
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void msix_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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int vector;
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bool was_masked;
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if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
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return;
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}
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trace_msix_write_config(dev->name, msix_enabled(dev), msix_masked(dev));
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was_masked = dev->msix_function_masked;
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msix_update_function_masked(dev);
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if (!msix_enabled(dev)) {
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return;
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}
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pci_device_deassert_intx(dev);
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if (dev->msix_function_masked == was_masked) {
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return;
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}
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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msix_handle_mask_update(dev, vector,
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msix_vector_masked(dev, vector, was_masked));
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}
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}
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static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIDevice *dev = opaque;
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return pci_get_long(dev->msix_table + addr);
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}
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static void msix_table_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIDevice *dev = opaque;
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int vector = addr / PCI_MSIX_ENTRY_SIZE;
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bool was_masked;
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was_masked = msix_is_masked(dev, vector);
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pci_set_long(dev->msix_table + addr, val);
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msix_handle_mask_update(dev, vector, was_masked);
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}
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static const MemoryRegionOps msix_table_mmio_ops = {
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.read = msix_table_mmio_read,
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.write = msix_table_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIDevice *dev = opaque;
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if (dev->msix_vector_poll_notifier) {
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unsigned vector_start = addr * 8;
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unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
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dev->msix_vector_poll_notifier(dev, vector_start, vector_end);
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}
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return pci_get_long(dev->msix_pba + addr);
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}
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static void msix_pba_mmio_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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}
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static const MemoryRegionOps msix_pba_mmio_ops = {
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.read = msix_pba_mmio_read,
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.write = msix_pba_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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{
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int vector;
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for (vector = 0; vector < nentries; ++vector) {
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unsigned offset =
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vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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bool was_masked = msix_is_masked(dev, vector);
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dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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msix_handle_mask_update(dev, vector, was_masked);
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}
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}
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/*
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* Make PCI device @dev MSI-X capable
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* @nentries is the max number of MSI-X vectors that the device support.
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* @table_bar is the MemoryRegion that MSI-X table structure resides.
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* @table_bar_nr is number of base address register corresponding to @table_bar.
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* @table_offset indicates the offset that the MSI-X table structure starts with
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* in @table_bar.
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* @pba_bar is the MemoryRegion that the Pending Bit Array structure resides.
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* @pba_bar_nr is number of base address register corresponding to @pba_bar.
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* @pba_offset indicates the offset that the Pending Bit Array structure
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* starts with in @pba_bar.
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* Non-zero @cap_pos puts capability MSI-X at that offset in PCI config space.
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* @errp is for returning errors.
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*
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* Return 0 on success; set @errp and return -errno on error:
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* -ENOTSUP means lacking msi support for a msi-capable platform.
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* -EINVAL means capability overlap, happens when @cap_pos is non-zero,
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* also means a programming error, except device assignment, which can check
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* if a real HW is broken.
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*/
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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MemoryRegion *table_bar, uint8_t table_bar_nr,
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unsigned table_offset, MemoryRegion *pba_bar,
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uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos,
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Error **errp)
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{
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int cap;
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unsigned table_size, pba_size;
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uint8_t *config;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msi_nonbroken) {
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error_setg(errp, "MSI-X is not supported by interrupt controller");
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return -ENOTSUP;
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}
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
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error_setg(errp, "The number of MSI-X vectors is invalid");
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return -EINVAL;
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}
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table_size = nentries * PCI_MSIX_ENTRY_SIZE;
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pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
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/* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
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if ((table_bar_nr == pba_bar_nr &&
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ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
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table_offset + table_size > memory_region_size(table_bar) ||
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pba_offset + pba_size > memory_region_size(pba_bar) ||
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(table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
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error_setg(errp, "table & pba overlap, or they don't fit in BARs,"
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" or don't align");
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return -EINVAL;
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}
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cap = pci_add_capability(dev, PCI_CAP_ID_MSIX,
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cap_pos, MSIX_CAP_LENGTH, errp);
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if (cap < 0) {
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return cap;
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}
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dev->msix_cap = cap;
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dev->cap_present |= QEMU_PCI_CAP_MSIX;
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config = dev->config + cap;
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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dev->msix_entries_nr = nentries;
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dev->msix_function_masked = true;
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pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
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pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
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/* Make flags bit writable. */
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dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
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MSIX_MASKALL_MASK;
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dev->msix_table = g_malloc0(table_size);
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dev->msix_pba = g_malloc0(pba_size);
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dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
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msix_mask_all(dev, nentries);
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memory_region_init_io(&dev->msix_table_mmio, OBJECT(dev), &msix_table_mmio_ops, dev,
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"msix-table", table_size);
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memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
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memory_region_init_io(&dev->msix_pba_mmio, OBJECT(dev), &msix_pba_mmio_ops, dev,
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"msix-pba", pba_size);
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memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
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return 0;
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}
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int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
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uint8_t bar_nr, Error **errp)
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{
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int ret;
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char *name;
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uint32_t bar_size = 4096;
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uint32_t bar_pba_offset = bar_size / 2;
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uint32_t bar_pba_size = (nentries / 8 + 1) * 8;
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/*
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* Migration compatibility dictates that this remains a 4k
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* BAR with the vector table in the lower half and PBA in
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* the upper half for nentries which is lower or equal to 128.
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* No need to care about using more than 65 entries for legacy
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* machine types who has at most 64 queues.
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*/
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if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
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bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
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}
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if (bar_pba_offset + bar_pba_size > 4096) {
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bar_size = bar_pba_offset + bar_pba_size;
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}
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bar_size = pow2ceil(bar_size);
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name = g_strdup_printf("%s-msix", dev->name);
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memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);
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g_free(name);
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ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
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0, &dev->msix_exclusive_bar,
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bar_nr, bar_pba_offset,
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0, errp);
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if (ret) {
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return ret;
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}
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pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
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&dev->msix_exclusive_bar);
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return 0;
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}
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static void msix_free_irq_entries(PCIDevice *dev)
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{
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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dev->msix_entry_used[vector] = 0;
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msix_clr_pending(dev, vector);
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}
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}
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static void msix_clear_all_vectors(PCIDevice *dev)
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{
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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msix_clr_pending(dev, vector);
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}
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}
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/* Clean up resources for the device. */
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void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
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{
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if (!msix_present(dev)) {
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return;
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}
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pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
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dev->msix_cap = 0;
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msix_free_irq_entries(dev);
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dev->msix_entries_nr = 0;
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memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
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g_free(dev->msix_pba);
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dev->msix_pba = NULL;
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memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
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g_free(dev->msix_table);
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dev->msix_table = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
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}
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void msix_uninit_exclusive_bar(PCIDevice *dev)
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{
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if (msix_present(dev)) {
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msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
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}
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}
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void msix_save(PCIDevice *dev, QEMUFile *f)
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{
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unsigned n = dev->msix_entries_nr;
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if (!msix_present(dev)) {
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return;
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}
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qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
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}
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/* Should be called after restoring the config space. */
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void msix_load(PCIDevice *dev, QEMUFile *f)
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{
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unsigned n = dev->msix_entries_nr;
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unsigned int vector;
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if (!msix_present(dev)) {
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return;
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}
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msix_clear_all_vectors(dev);
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qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
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msix_update_function_masked(dev);
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for (vector = 0; vector < n; vector++) {
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msix_handle_mask_update(dev, vector, true);
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}
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}
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/* Does device support MSI-X? */
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int msix_present(PCIDevice *dev)
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{
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return dev->cap_present & QEMU_PCI_CAP_MSIX;
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}
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/* Is MSI-X enabled? */
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int msix_enabled(PCIDevice *dev)
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{
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return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
|
MSIX_ENABLE_MASK);
|
|
}
|
|
|
|
/* Send an MSI-X message */
|
|
void msix_notify(PCIDevice *dev, unsigned vector)
|
|
{
|
|
MSIMessage msg;
|
|
|
|
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
|
return;
|
|
}
|
|
|
|
if (msix_is_masked(dev, vector)) {
|
|
msix_set_pending(dev, vector);
|
|
return;
|
|
}
|
|
|
|
msg = msix_get_message(dev, vector);
|
|
|
|
msi_send_message(dev, msg);
|
|
}
|
|
|
|
void msix_reset(PCIDevice *dev)
|
|
{
|
|
if (!msix_present(dev)) {
|
|
return;
|
|
}
|
|
msix_clear_all_vectors(dev);
|
|
dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
|
|
~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
|
|
memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
|
|
memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
|
|
msix_mask_all(dev, dev->msix_entries_nr);
|
|
}
|
|
|
|
/* PCI spec suggests that devices make it possible for software to configure
|
|
* less vectors than supported by the device, but does not specify a standard
|
|
* mechanism for devices to do so.
|
|
*
|
|
* We support this by asking devices to declare vectors software is going to
|
|
* actually use, and checking this on the notification path. Devices that
|
|
* don't want to follow the spec suggestion can declare all vectors as used. */
|
|
|
|
/* Mark vector as used. */
|
|
int msix_vector_use(PCIDevice *dev, unsigned vector)
|
|
{
|
|
if (vector >= dev->msix_entries_nr) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev->msix_entry_used[vector]++;
|
|
return 0;
|
|
}
|
|
|
|
/* Mark vector as unused. */
|
|
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
|
|
{
|
|
if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
|
|
return;
|
|
}
|
|
if (--dev->msix_entry_used[vector]) {
|
|
return;
|
|
}
|
|
msix_clr_pending(dev, vector);
|
|
}
|
|
|
|
void msix_unuse_all_vectors(PCIDevice *dev)
|
|
{
|
|
if (!msix_present(dev)) {
|
|
return;
|
|
}
|
|
msix_free_irq_entries(dev);
|
|
}
|
|
|
|
unsigned int msix_nr_vectors_allocated(const PCIDevice *dev)
|
|
{
|
|
return dev->msix_entries_nr;
|
|
}
|
|
|
|
static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
|
|
{
|
|
MSIMessage msg;
|
|
|
|
if (msix_is_masked(dev, vector)) {
|
|
return 0;
|
|
}
|
|
msg = msix_get_message(dev, vector);
|
|
return dev->msix_vector_use_notifier(dev, vector, msg);
|
|
}
|
|
|
|
static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
|
|
{
|
|
if (msix_is_masked(dev, vector)) {
|
|
return;
|
|
}
|
|
dev->msix_vector_release_notifier(dev, vector);
|
|
}
|
|
|
|
int msix_set_vector_notifiers(PCIDevice *dev,
|
|
MSIVectorUseNotifier use_notifier,
|
|
MSIVectorReleaseNotifier release_notifier,
|
|
MSIVectorPollNotifier poll_notifier)
|
|
{
|
|
int vector, ret;
|
|
|
|
assert(use_notifier && release_notifier);
|
|
|
|
dev->msix_vector_use_notifier = use_notifier;
|
|
dev->msix_vector_release_notifier = release_notifier;
|
|
dev->msix_vector_poll_notifier = poll_notifier;
|
|
|
|
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
|
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
|
|
for (vector = 0; vector < dev->msix_entries_nr; vector++) {
|
|
ret = msix_set_notifier_for_vector(dev, vector);
|
|
if (ret < 0) {
|
|
goto undo;
|
|
}
|
|
}
|
|
}
|
|
if (dev->msix_vector_poll_notifier) {
|
|
dev->msix_vector_poll_notifier(dev, 0, dev->msix_entries_nr);
|
|
}
|
|
return 0;
|
|
|
|
undo:
|
|
while (--vector >= 0) {
|
|
msix_unset_notifier_for_vector(dev, vector);
|
|
}
|
|
dev->msix_vector_use_notifier = NULL;
|
|
dev->msix_vector_release_notifier = NULL;
|
|
return ret;
|
|
}
|
|
|
|
void msix_unset_vector_notifiers(PCIDevice *dev)
|
|
{
|
|
int vector;
|
|
|
|
assert(dev->msix_vector_use_notifier &&
|
|
dev->msix_vector_release_notifier);
|
|
|
|
if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
|
|
(MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
|
|
for (vector = 0; vector < dev->msix_entries_nr; vector++) {
|
|
msix_unset_notifier_for_vector(dev, vector);
|
|
}
|
|
}
|
|
dev->msix_vector_use_notifier = NULL;
|
|
dev->msix_vector_release_notifier = NULL;
|
|
dev->msix_vector_poll_notifier = NULL;
|
|
}
|
|
|
|
static int put_msix_state(QEMUFile *f, void *pv, size_t size,
|
|
VMStateField *field, QJSON *vmdesc)
|
|
{
|
|
msix_save(pv, f);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int get_msix_state(QEMUFile *f, void *pv, size_t size,
|
|
VMStateField *field)
|
|
{
|
|
msix_load(pv, f);
|
|
return 0;
|
|
}
|
|
|
|
static VMStateInfo vmstate_info_msix = {
|
|
.name = "msix state",
|
|
.get = get_msix_state,
|
|
.put = put_msix_state,
|
|
};
|
|
|
|
const VMStateDescription vmstate_msix = {
|
|
.name = "msix",
|
|
.fields = (VMStateField[]) {
|
|
{
|
|
.name = "msix",
|
|
.version_id = 0,
|
|
.field_exists = NULL,
|
|
.size = 0, /* ouch */
|
|
.info = &vmstate_info_msix,
|
|
.flags = VMS_SINGLE,
|
|
.offset = 0,
|
|
},
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|