133 lines
3.8 KiB
C
133 lines
3.8 KiB
C
/*
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* Internal execution defines for qemu (target specific)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef ACCEL_TCG_INTERNAL_TARGET_H
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#define ACCEL_TCG_INTERNAL_TARGET_H
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#include "exec/exec-all.h"
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#include "exec/translate-all.h"
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/*
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* Access to the various translations structures need to be serialised
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* via locks for consistency. In user-mode emulation access to the
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* memory related structures are protected with mmap_lock.
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* In !user-mode we use per-page locks.
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*/
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#ifdef CONFIG_USER_ONLY
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#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
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#else
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#define assert_memory_lock()
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#endif
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#if defined(CONFIG_SOFTMMU) && defined(CONFIG_DEBUG_TCG)
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void assert_no_pages_locked(void);
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#else
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static inline void assert_no_pages_locked(void) { }
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#endif
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#ifdef CONFIG_USER_ONLY
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static inline void page_table_config_init(void) { }
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#else
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void page_table_config_init(void);
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#endif
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#ifdef CONFIG_USER_ONLY
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/*
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* For user-only, page_protect sets the page read-only.
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* Since most execution is already on read-only pages, and we'd need to
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* account for other TBs on the same page, defer undoing any page protection
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* until we receive the write fault.
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*/
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static inline void tb_lock_page0(tb_page_addr_t p0)
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{
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page_protect(p0);
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}
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static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1)
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{
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page_protect(p1);
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}
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static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { }
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static inline void tb_unlock_pages(TranslationBlock *tb) { }
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#else
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void tb_lock_page0(tb_page_addr_t);
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void tb_lock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t);
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void tb_unlock_pages(TranslationBlock *);
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#endif
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#ifdef CONFIG_SOFTMMU
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void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
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unsigned size,
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uintptr_t retaddr);
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G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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#endif /* CONFIG_SOFTMMU */
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TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc,
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uint64_t cs_base, uint32_t flags,
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int cflags);
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void page_init(void);
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void tb_htable_init(void);
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void tb_reset_jump(TranslationBlock *tb, int n);
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TranslationBlock *tb_link_page(TranslationBlock *tb);
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bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
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void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
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uintptr_t host_pc);
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bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
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void tcg_exec_unrealizefn(CPUState *cpu);
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/* Return the current PC from CPU, which may be cached in TB. */
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static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb)
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{
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if (tb_cflags(tb) & CF_PCREL) {
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return cpu->cc->get_pc(cpu);
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} else {
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return tb->pc;
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}
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}
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extern bool one_insn_per_tb;
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/**
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* tcg_req_mo:
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* @type: TCGBar
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*
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* Filter @type to the barrier that is required for the guest
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* memory ordering vs the host memory ordering. A non-zero
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* result indicates that some barrier is required.
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*
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* If TCG_GUEST_DEFAULT_MO is not defined, assume that the
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* guest requires strict ordering.
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*
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* This is a macro so that it's constant even without optimization.
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*/
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#ifdef TCG_GUEST_DEFAULT_MO
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# define tcg_req_mo(type) \
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((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
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#else
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# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
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#endif
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/**
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* cpu_req_mo:
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* @type: TCGBar
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*
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* If tcg_req_mo indicates a barrier for @type is required
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* for the guest memory model, issue a host memory barrier.
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*/
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#define cpu_req_mo(type) \
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do { \
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if (tcg_req_mo(type)) { \
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smp_mb(); \
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} \
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} while (0)
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#endif /* ACCEL_TCG_INTERNAL_H */
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