Conor Dooley 8d32e374a8 hw/riscv: pfsoc: add missing FICs as unimplemented ... The Fabric Interconnect Controllers provide interfaces between the FPGA fabric and the core complex. There are 5 FICs on PolarFire SoC, numbered 0 through 4. FIC2 is an AXI4 slave interface from the FPGA fabric and does not show up on the MSS memory map. FIC4 is dedicated to the User Crypto Processor and does not show up on the MSS memory map either. FIC 0, 1 & 3 do show up in the MSS memory map and neither FICs 0 or 1 are represented in QEMU, leading to load access violations while booting Linux for Icicle if PCIe is enabled as the root port is connected via either FIC 0 or 1. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20221117225518.4102575-3-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-01-06 10:42:55 +10:00
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boot_opensbi.h
boot.h	hw/riscv: virt: Enable booting S-mode firmware from pflash	2022-10-14 14:29:50 +10:00
microchip_pfsoc.h	hw/riscv: pfsoc: add missing FICs as unimplemented	2023-01-06 10:42:55 +10:00
numa.h
opentitan.h	hw/riscv/opentitan: add aon_timer base unimpl	2023-01-06 10:42:55 +10:00
riscv_hart.h
shakti_c.h
sifive_cpu.h
sifive_e.h	hw/riscv/sifive_e: Fix inheritance of SiFiveEState	2022-09-27 07:04:38 +10:00
sifive_u.h
spike.h
virt.h	hw/riscv: virt: Remove the redundant ipi-id property	2023-01-06 10:42:55 +10:00