OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
qemu-e2k/target/arm
History
Peter Maydell 8e228c9e4b target/arm: Implement HSTR.TJDBX 
In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1
access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ.
Implement these traps. In v8A this HSTR bit doesn't exist, so don't
trap for v8A CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-3-peter.maydell@linaro.org
2021-08-26 17:02:01 +01:00
..
a32-uncond.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
a32.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
arch_dump.c
target/arm: add spaces around operator
2020-11-10 11:03:47 +00:00
arm_ldst.h
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
arm-powerctl.c
arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()
2019-12-20 14:03:00 +00:00
arm-powerctl.h
target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
2019-02-28 11:03:04 +00:00
cpu64.c
target/arm/cpu64: Validate sve vector lengths are supported
2021-08-26 17:01:59 +01:00
cpu_tcg.c
target/arm: Implement debug_check_breakpoint
2021-07-21 07:47:04 -10:00
cpu-param.h
linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
2021-02-16 13:06:16 +00:00
cpu-qom.h
qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
2020-09-18 14:12:32 -04:00
cpu.c
target/arm: Avoid assertion trying to use KVM and multiple ASes
2021-08-26 17:02:01 +01:00
cpu.h
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
crypto_helper.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
debug_helper.c
accel/tcg: Remove TranslatorOps.breakpoint_check
2021-07-21 07:47:05 -10:00
gdbstub64.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
gdbstub.c
target/arm: Enforce that M-profile SP low 2 bits are always zero
2021-07-27 10:57:39 +01:00
helper-a64.c
tcg: Rename helper_atomic_*_mmu and provide for user-only
2021-07-21 07:45:38 -10:00
helper-a64.h
target/arm: Merge mte_check1, mte_checkN
2021-04-30 11:16:49 +01:00
helper-mve.h
target/arm: Implement MVE interleaving loads/stores
2021-08-25 10:48:50 +01:00
helper-sve.h
target/arm: Implement vector float32 to bfloat16 conversion
2021-06-03 16:43:26 +01:00
helper.c
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
helper.h
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
idau.h
Use DECLARE_*CHECKER* macros
2020-09-09 09:27:09 -04:00
internals.h
target/arm: Export aarch64_sve_zcr_get_valid_len
2021-07-27 10:57:40 +01:00
iwmmxt_helper.c
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
kvm64.c
target/arm/kvm64: Ensure sve vls map is completely clear
2021-08-26 17:01:59 +01:00
kvm_arm.h
hw/arm/virt: KVM: The IPA lower bound is 32
2021-03-12 12:47:11 +00:00
kvm-consts.h
target/arm: Remove no-longer-reachable 32-bit KVM code
2020-09-14 14:23:19 +01:00
kvm-stub.c
Include qemu-common.h exactly where needed
2019-06-12 13:20:20 +02:00
kvm.c
target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
2021-08-25 10:48:50 +01:00
m_helper.c
target/arm: Implement M-profile trapping on division by zero
2021-08-25 10:48:50 +01:00
m-nocp.decode
target/arm: Don't NOCP fault for FPCXT_NS accesses
2021-06-21 16:49:37 +01:00
machine.c
target/arm: Make FPSCR.LTPSIZE writable for MVE
2021-06-03 16:43:25 +01:00
meson.build
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
2021-06-21 16:49:38 +01:00
monitor.c
target/arm: Add cpu properties to control pauth
2021-01-19 14:38:51 +00:00
mte_helper.c
target/arm: Implement MTE3
2021-06-24 14:58:48 +01:00
mve_helper.c
target/arm: Implement MVE interleaving loads/stores
2021-08-25 10:48:50 +01:00
mve.decode
target/arm: Implement MVE interleaving loads/stores
2021-08-25 10:48:50 +01:00
neon_helper.c
target/arm: Split out saturating/rounding shifts from neon
2021-05-25 16:01:43 +01:00
neon-dp.decode
target/arm: Implement vector float32 to bfloat16 conversion
2021-06-03 16:43:26 +01:00
neon-ls.decode
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
2021-07-18 10:59:47 +01:00
neon-shared.decode
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
2021-07-18 10:59:47 +01:00
op_addsub.h
Move target-* CPU file into a target/ folder
2016-12-20 21:52:12 +01:00
op_helper.c
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
pauth_helper.c
target/arm: Implement an IMPDEF pauth algorithm
2021-01-19 14:38:51 +00:00
psci.c
sysemu: Split sysemu/runstate.h off sysemu/sysemu.h
2019-08-16 13:37:36 +02:00
sve_helper.c
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
2021-06-16 14:33:52 +01:00
sve.decode
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
2021-07-18 10:59:47 +01:00
syndrome.h
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
t16.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
t32.decode
target/arm: Implement MVE VCTP
2021-08-25 10:48:50 +01:00
tlb_helper.c
target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill
2021-03-23 14:07:55 +00:00
trace-events
docs: fix references to docs/devel/tracing.rst
2021-06-02 06:51:09 +02:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate-a32.h
target/arm: Implement MVE VCTP
2021-08-25 10:48:50 +01:00
translate-a64.c
accel/tcg: Remove TranslatorOps.breakpoint_check
2021-07-21 07:47:05 -10:00
translate-a64.h
target/arm: Implement SVE2 XAR
2021-05-25 16:01:44 +01:00
translate-m-nocp.c
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
2021-06-21 16:49:38 +01:00
translate-mve.c
target/arm: Implement MVE interleaving loads/stores
2021-08-25 10:48:50 +01:00
translate-neon.c
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
2021-07-18 10:59:47 +01:00
translate-sve.c
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
2021-07-18 10:59:47 +01:00
translate-vfp.c
target/arm: Implement MVE VMOV to/from 2 general-purpose registers
2021-08-25 10:48:50 +01:00
translate.c
target/arm: Implement HSTR.TJDBX
2021-08-26 17:02:01 +01:00
translate.h
target/arm: Implement MVE shifts by register
2021-07-02 11:48:38 +01:00
vec_helper.c
target/arm: Implement MVE VMULL (polynomial)
2021-08-25 10:48:49 +01:00
vec_internal.h
target/arm: Implement MVE VMULL (polynomial)
2021-08-25 10:48:49 +01:00
vfp_helper.c
target/arm: Check NaN mode before silencing NaN
2021-07-02 11:48:36 +01:00
vfp-uncond.decode
arm tcg cpus: Fix Lesser GPL version number
2020-11-15 16:42:14 +01:00
vfp.decode
target/arm: Don't NOCP fault for FPCXT_NS accesses
2021-06-21 16:49:37 +01:00