267 lines
7.3 KiB
C
267 lines
7.3 KiB
C
#ifndef HW_NVME_H
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#define HW_NVME_H
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#include "block/nvme.h"
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#include "hw/pci/pci.h"
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#include "nvme-subsys.h"
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#include "nvme-ns.h"
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#define NVME_DEFAULT_ZONE_SIZE (128 * MiB)
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#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB)
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typedef struct NvmeParams {
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char *serial;
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uint32_t num_queues; /* deprecated since 5.1 */
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uint32_t max_ioqpairs;
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uint16_t msix_qsize;
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uint32_t cmb_size_mb;
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uint8_t aerl;
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uint32_t aer_max_queued;
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uint8_t mdts;
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uint8_t vsl;
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bool use_intel_id;
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uint8_t zasl;
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bool legacy_cmb;
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} NvmeParams;
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typedef struct NvmeAsyncEvent {
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QTAILQ_ENTRY(NvmeAsyncEvent) entry;
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NvmeAerResult result;
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} NvmeAsyncEvent;
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enum {
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NVME_SG_ALLOC = 1 << 0,
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NVME_SG_DMA = 1 << 1,
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};
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typedef struct NvmeSg {
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int flags;
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union {
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QEMUSGList qsg;
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QEMUIOVector iov;
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};
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} NvmeSg;
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typedef struct NvmeRequest {
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struct NvmeSQueue *sq;
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struct NvmeNamespace *ns;
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BlockAIOCB *aiocb;
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uint16_t status;
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void *opaque;
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NvmeCqe cqe;
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NvmeCmd cmd;
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BlockAcctCookie acct;
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NvmeSg sg;
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QTAILQ_ENTRY(NvmeRequest)entry;
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} NvmeRequest;
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typedef struct NvmeBounceContext {
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NvmeRequest *req;
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struct {
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QEMUIOVector iov;
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uint8_t *bounce;
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} data, mdata;
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} NvmeBounceContext;
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static inline const char *nvme_adm_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_ADM_CMD_DELETE_SQ: return "NVME_ADM_CMD_DELETE_SQ";
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case NVME_ADM_CMD_CREATE_SQ: return "NVME_ADM_CMD_CREATE_SQ";
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case NVME_ADM_CMD_GET_LOG_PAGE: return "NVME_ADM_CMD_GET_LOG_PAGE";
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case NVME_ADM_CMD_DELETE_CQ: return "NVME_ADM_CMD_DELETE_CQ";
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case NVME_ADM_CMD_CREATE_CQ: return "NVME_ADM_CMD_CREATE_CQ";
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case NVME_ADM_CMD_IDENTIFY: return "NVME_ADM_CMD_IDENTIFY";
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case NVME_ADM_CMD_ABORT: return "NVME_ADM_CMD_ABORT";
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case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
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case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
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case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
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case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
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case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
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default: return "NVME_ADM_CMD_UNKNOWN";
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}
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}
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static inline const char *nvme_io_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH";
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case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE";
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case NVME_CMD_READ: return "NVME_NVM_CMD_READ";
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case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE";
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case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
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case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM";
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case NVME_CMD_VERIFY: return "NVME_NVM_CMD_VERIFY";
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case NVME_CMD_COPY: return "NVME_NVM_CMD_COPY";
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case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_MGMT_SEND";
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case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_MGMT_RECV";
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case NVME_CMD_ZONE_APPEND: return "NVME_ZONED_CMD_ZONE_APPEND";
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default: return "NVME_NVM_CMD_UNKNOWN";
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}
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}
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typedef struct NvmeSQueue {
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struct NvmeCtrl *ctrl;
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uint16_t sqid;
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uint16_t cqid;
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uint32_t head;
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uint32_t tail;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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NvmeRequest *io_req;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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QTAILQ_HEAD(, NvmeRequest) out_req_list;
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QTAILQ_ENTRY(NvmeSQueue) entry;
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} NvmeSQueue;
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typedef struct NvmeCQueue {
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struct NvmeCtrl *ctrl;
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uint8_t phase;
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uint16_t cqid;
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uint16_t irq_enabled;
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uint32_t head;
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uint32_t tail;
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uint32_t vector;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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QTAILQ_HEAD(, NvmeSQueue) sq_list;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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} NvmeCQueue;
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#define TYPE_NVME_BUS "nvme-bus"
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#define NVME_BUS(obj) OBJECT_CHECK(NvmeBus, (obj), TYPE_NVME_BUS)
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typedef struct NvmeBus {
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BusState parent_bus;
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} NvmeBus;
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#define TYPE_NVME "nvme"
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#define NVME(obj) \
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OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
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typedef struct NvmeFeatureVal {
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struct {
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uint16_t temp_thresh_hi;
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uint16_t temp_thresh_low;
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};
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uint32_t async_config;
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} NvmeFeatureVal;
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typedef struct NvmeCtrl {
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PCIDevice parent_obj;
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MemoryRegion bar0;
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MemoryRegion iomem;
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NvmeBar bar;
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NvmeParams params;
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NvmeBus bus;
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uint16_t cntlid;
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bool qs_created;
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uint32_t page_size;
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uint16_t page_bits;
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uint16_t max_prp_ents;
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uint16_t cqe_size;
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uint16_t sqe_size;
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uint32_t reg_size;
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uint32_t num_namespaces;
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uint32_t max_q_ents;
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uint8_t outstanding_aers;
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uint32_t irq_status;
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uint64_t host_timestamp; /* Timestamp sent by the host */
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uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
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uint64_t starttime_ms;
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uint16_t temperature;
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uint8_t smart_critical_warning;
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struct {
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MemoryRegion mem;
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uint8_t *buf;
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bool cmse;
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hwaddr cba;
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} cmb;
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struct {
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HostMemoryBackend *dev;
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bool cmse;
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hwaddr cba;
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} pmr;
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uint8_t aer_mask;
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NvmeRequest **aer_reqs;
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QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
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int aer_queued;
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uint32_t dmrsl;
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/* Namespace ID is started with 1 so bitmap should be 1-based */
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#define NVME_CHANGED_NSID_SIZE (NVME_MAX_NAMESPACES + 1)
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DECLARE_BITMAP(changed_nsids, NVME_CHANGED_NSID_SIZE);
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NvmeSubsystem *subsys;
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NvmeNamespace namespace;
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/*
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* Attached namespaces to this controller. If subsys is not given, all
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* namespaces in this list will always be attached.
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*/
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES];
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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NvmeSQueue admin_sq;
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NvmeCQueue admin_cq;
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NvmeIdCtrl id_ctrl;
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NvmeFeatureVal features;
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} NvmeCtrl;
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static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
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{
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if (!nsid || nsid > n->num_namespaces) {
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return NULL;
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}
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return n->namespaces[nsid - 1];
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}
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static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
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{
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NvmeSQueue *sq = req->sq;
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NvmeCtrl *n = sq->ctrl;
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return n->cq[sq->cqid];
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}
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static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
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{
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NvmeSQueue *sq = req->sq;
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return sq->ctrl;
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}
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static inline uint16_t nvme_cid(NvmeRequest *req)
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{
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if (!req) {
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return 0xffff;
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}
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return le16_to_cpu(req->cqe.cid);
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}
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typedef enum NvmeTxDirection {
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NVME_TX_DIRECTION_TO_DEVICE = 0,
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NVME_TX_DIRECTION_FROM_DEVICE = 1,
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} NvmeTxDirection;
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void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns);
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uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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NvmeTxDirection dir, NvmeRequest *req);
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uint16_t nvme_bounce_mdata(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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NvmeTxDirection dir, NvmeRequest *req);
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void nvme_rw_complete_cb(void *opaque, int ret);
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uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
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NvmeCmd *cmd);
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#endif /* HW_NVME_H */
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