5bddf92e68
On some boards, SCC config register CFG0 bit 0 controls whether parts of the board memory map are remapped. Support this with: * a device property scc-cfg0 so the board can specify the initial value of the CFG0 register * an outbound GPIO line which tracks bit 0 and which the board can wire up to provide the remapping Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
397 lines
12 KiB
C
397 lines
12 KiB
C
/*
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* ARM MPS2 SCC emulation
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*
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* Copyright (c) 2017 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the SCC (Serial Communication Controller)
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* found in the FPGA images of MPS2 development boards.
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*
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* Documentation of it can be found in the MPS2 TRM:
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* https://developer.arm.com/documentation/100112/latest/
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* and also in the Application Notes documenting individual FPGA images.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/misc/mps2-scc.h"
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#include "hw/misc/led.h"
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#include "hw/qdev-properties.h"
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REG32(CFG0, 0)
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REG32(CFG1, 4)
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REG32(CFG2, 8)
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REG32(CFG3, 0xc)
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REG32(CFG4, 0x10)
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REG32(CFG5, 0x14)
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REG32(CFG6, 0x18)
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REG32(CFGDATA_RTN, 0xa0)
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REG32(CFGDATA_OUT, 0xa4)
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REG32(CFGCTRL, 0xa8)
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FIELD(CFGCTRL, DEVICE, 0, 12)
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FIELD(CFGCTRL, RES1, 12, 8)
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FIELD(CFGCTRL, FUNCTION, 20, 6)
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FIELD(CFGCTRL, RES2, 26, 4)
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FIELD(CFGCTRL, WRITE, 30, 1)
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FIELD(CFGCTRL, START, 31, 1)
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REG32(CFGSTAT, 0xac)
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FIELD(CFGSTAT, DONE, 0, 1)
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FIELD(CFGSTAT, ERROR, 1, 1)
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REG32(DLL, 0x100)
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REG32(AID, 0xFF8)
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REG32(ID, 0xFFC)
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static int scc_partno(MPS2SCC *s)
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{
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/* Return the partno field of the SCC_ID (0x524, 0x511, etc) */
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return extract32(s->id, 4, 8);
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}
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/* Handle a write via the SYS_CFG channel to the specified function/device.
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* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
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*/
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static bool scc_cfg_write(MPS2SCC *s, unsigned function,
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unsigned device, uint32_t value)
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{
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trace_mps2_scc_cfg_write(function, device, value);
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if (function != 1 || device >= s->num_oscclk) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 SCC config write: bad function %d device %d\n",
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function, device);
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return false;
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}
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s->oscclk[device] = value;
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return true;
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}
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/* Handle a read via the SYS_CFG channel to the specified function/device.
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* Return false on error (reported to guest via SYS_CFGCTRL ERROR bit),
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* or set *value on success.
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*/
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static bool scc_cfg_read(MPS2SCC *s, unsigned function,
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unsigned device, uint32_t *value)
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{
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if (function != 1 || device >= s->num_oscclk) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 SCC config read: bad function %d device %d\n",
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function, device);
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return false;
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}
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*value = s->oscclk[device];
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trace_mps2_scc_cfg_read(function, device, *value);
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return true;
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}
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static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
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{
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MPS2SCC *s = MPS2_SCC(opaque);
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uint64_t r;
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switch (offset) {
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case A_CFG0:
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r = s->cfg0;
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break;
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case A_CFG1:
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r = s->cfg1;
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break;
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case A_CFG2:
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG2 reserved on other boards */
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goto bad_offset;
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}
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r = s->cfg2;
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break;
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case A_CFG3:
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if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
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/* CFG3 reserved on AN524 */
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goto bad_offset;
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}
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/* These are user-settable DIP switches on the board. We don't
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* model that, so just return zeroes.
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*/
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r = 0;
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break;
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case A_CFG4:
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r = s->cfg4;
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break;
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case A_CFG5:
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG5 reserved on other boards */
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goto bad_offset;
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}
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r = s->cfg5;
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break;
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case A_CFG6:
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if (scc_partno(s) != 0x524) {
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/* CFG6 reserved on other boards */
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goto bad_offset;
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}
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r = s->cfg6;
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break;
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case A_CFGDATA_RTN:
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r = s->cfgdata_rtn;
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break;
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case A_CFGDATA_OUT:
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r = s->cfgdata_out;
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break;
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case A_CFGCTRL:
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r = s->cfgctrl;
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break;
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case A_CFGSTAT:
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r = s->cfgstat;
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break;
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case A_DLL:
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r = s->dll;
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break;
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case A_AID:
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r = s->aid;
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break;
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case A_ID:
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r = s->id;
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 SCC read: bad offset %x\n", (int) offset);
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r = 0;
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break;
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}
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trace_mps2_scc_read(offset, r, size);
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return r;
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}
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static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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MPS2SCC *s = MPS2_SCC(opaque);
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trace_mps2_scc_write(offset, value, size);
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switch (offset) {
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case A_CFG0:
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/*
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* On some boards bit 0 controls board-specific remapping;
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* we always reflect bit 0 in the 'remap' GPIO output line,
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* and let the board wire it up or not as it chooses.
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* TODO on some boards bit 1 is CPU_WAIT.
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*/
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s->cfg0 = value;
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qemu_set_irq(s->remap, s->cfg0 & 1);
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break;
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case A_CFG1:
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s->cfg1 = value;
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for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
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led_set_state(s->led[i], extract32(value, i, 1));
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}
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break;
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case A_CFG2:
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG2 reserved on other boards */
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goto bad_offset;
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}
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/* AN524: QSPI Select signal */
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s->cfg2 = value;
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break;
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case A_CFG5:
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if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
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/* CFG5 reserved on other boards */
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goto bad_offset;
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}
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/* AN524: ACLK frequency in Hz */
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s->cfg5 = value;
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break;
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case A_CFG6:
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if (scc_partno(s) != 0x524) {
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/* CFG6 reserved on other boards */
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goto bad_offset;
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}
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/* AN524: Clock divider for BRAM */
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s->cfg6 = value;
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break;
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case A_CFGDATA_OUT:
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s->cfgdata_out = value;
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break;
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case A_CFGCTRL:
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/* Writing to CFGCTRL clears SYS_CFGSTAT */
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s->cfgstat = 0;
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s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK |
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R_CFGCTRL_RES2_MASK |
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R_CFGCTRL_START_MASK);
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if (value & R_CFGCTRL_START_MASK) {
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/* Start bit set -- do a read or write (instantaneously) */
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int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT,
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R_CFGCTRL_DEVICE_LENGTH);
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int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT,
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R_CFGCTRL_FUNCTION_LENGTH);
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s->cfgstat = R_CFGSTAT_DONE_MASK;
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if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) {
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if (!scc_cfg_write(s, function, device, s->cfgdata_out)) {
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s->cfgstat |= R_CFGSTAT_ERROR_MASK;
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}
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} else {
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uint32_t result;
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if (!scc_cfg_read(s, function, device, &result)) {
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s->cfgstat |= R_CFGSTAT_ERROR_MASK;
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} else {
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s->cfgdata_rtn = result;
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}
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}
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}
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break;
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case A_DLL:
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/* DLL stands for Digital Locked Loop.
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* Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a
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* mask of which of the DLL_LOCKED bits [16:23] should be ORed
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* together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0].
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* For QEMU, our DLLs are always locked, so we can leave bit 0
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* as 1 always and don't need to recalculate it.
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*/
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s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 SCC write: bad offset 0x%x\n", (int) offset);
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break;
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}
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}
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static const MemoryRegionOps mps2_scc_ops = {
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.read = mps2_scc_read,
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.write = mps2_scc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mps2_scc_reset(DeviceState *dev)
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{
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MPS2SCC *s = MPS2_SCC(dev);
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int i;
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trace_mps2_scc_reset();
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s->cfg0 = s->cfg0_reset;
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s->cfg1 = 0;
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s->cfg2 = 0;
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s->cfg5 = 0;
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s->cfg6 = 0;
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s->cfgdata_rtn = 0;
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s->cfgdata_out = 0;
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s->cfgctrl = 0x100000;
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s->cfgstat = 0;
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s->dll = 0xffff0001;
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for (i = 0; i < s->num_oscclk; i++) {
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s->oscclk[i] = s->oscclk_reset[i];
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}
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for (i = 0; i < ARRAY_SIZE(s->led); i++) {
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device_cold_reset(DEVICE(s->led[i]));
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}
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}
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static void mps2_scc_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MPS2SCC *s = MPS2_SCC(obj);
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memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1);
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}
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static void mps2_scc_realize(DeviceState *dev, Error **errp)
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{
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MPS2SCC *s = MPS2_SCC(dev);
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for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
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char *name = g_strdup_printf("SCC LED%zu", i);
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s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
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LED_COLOR_GREEN, name);
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g_free(name);
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}
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s->oscclk = g_new0(uint32_t, s->num_oscclk);
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}
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static const VMStateDescription mps2_scc_vmstate = {
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.name = "mps2-scc",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cfg0, MPS2SCC),
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VMSTATE_UINT32(cfg1, MPS2SCC),
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VMSTATE_UINT32(cfg2, MPS2SCC),
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/* cfg3, cfg4 are read-only so need not be migrated */
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VMSTATE_UINT32(cfg5, MPS2SCC),
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VMSTATE_UINT32(cfg6, MPS2SCC),
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VMSTATE_UINT32(cfgdata_rtn, MPS2SCC),
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VMSTATE_UINT32(cfgdata_out, MPS2SCC),
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VMSTATE_UINT32(cfgctrl, MPS2SCC),
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VMSTATE_UINT32(cfgstat, MPS2SCC),
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VMSTATE_UINT32(dll, MPS2SCC),
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VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property mps2_scc_properties[] = {
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/* Values for various read-only ID registers (which are specific
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* to the board model or FPGA image)
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*/
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DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
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DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
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DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
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/* Reset value for CFG0 register */
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DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0),
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/*
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* These are the initial settings for the source clocks on the board.
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* In hardware they can be configured via a config file read by the
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* motherboard configuration controller to suit the FPGA image.
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*/
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DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset,
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qdev_prop_uint32, uint32_t),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mps2_scc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mps2_scc_realize;
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dc->vmsd = &mps2_scc_vmstate;
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dc->reset = mps2_scc_reset;
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device_class_set_props(dc, mps2_scc_properties);
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}
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static const TypeInfo mps2_scc_info = {
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.name = TYPE_MPS2_SCC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MPS2SCC),
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.instance_init = mps2_scc_init,
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.class_init = mps2_scc_class_init,
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};
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static void mps2_scc_register_types(void)
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{
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type_register_static(&mps2_scc_info);
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}
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type_init(mps2_scc_register_types);
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