39bffca203
This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
276 lines
7.4 KiB
C
276 lines
7.4 KiB
C
/*
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* QEMU Intel i82378 emulation (PCI to ISA bridge)
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*
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* Copyright (c) 2010-2011 Hervé Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "pci.h"
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#include "pc.h"
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//#define DEBUG_I82378
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#ifdef DEBUG_I82378
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do {} while (0)
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#endif
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
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typedef struct I82378State {
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qemu_irq out[2];
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qemu_irq *i8259;
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MemoryRegion io;
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MemoryRegion mem;
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} I82378State;
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typedef struct PCIi82378State {
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PCIDevice pci_dev;
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uint32_t isa_io_base;
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uint32_t isa_mem_base;
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I82378State state;
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} PCIi82378State;
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static const VMStateDescription vmstate_pci_i82378 = {
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.name = "pci-i82378",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
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VMSTATE_END_OF_LIST()
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},
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};
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static void i82378_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned int size)
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{
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switch (size) {
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case 1:
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DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
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addr, value);
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cpu_outb(addr, value);
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break;
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case 2:
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DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
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addr, value);
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cpu_outw(addr, value);
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break;
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case 4:
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DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
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addr, value);
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cpu_outl(addr, value);
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break;
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default:
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abort();
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}
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}
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static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
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switch (size) {
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case 1:
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return cpu_inb(addr);
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case 2:
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return cpu_inw(addr);
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case 4:
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return cpu_inl(addr);
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default:
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abort();
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}
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}
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static const MemoryRegionOps i82378_io_ops = {
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.read = i82378_io_read,
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.write = i82378_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned int size)
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{
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switch (size) {
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case 1:
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DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
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addr, value);
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cpu_outb(addr, value);
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break;
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case 2:
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DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
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addr, value);
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cpu_outw(addr, value);
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break;
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case 4:
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DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
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addr, value);
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cpu_outl(addr, value);
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break;
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default:
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abort();
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}
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}
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static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
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switch (size) {
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case 1:
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return cpu_inb(addr);
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case 2:
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return cpu_inw(addr);
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case 4:
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return cpu_inl(addr);
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default:
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abort();
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}
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}
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static const MemoryRegionOps i82378_mem_ops = {
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.read = i82378_mem_read,
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.write = i82378_mem_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void i82378_request_out0_irq(void *opaque, int irq, int level)
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{
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I82378State *s = opaque;
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qemu_set_irq(s->out[0], level);
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}
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static void i82378_request_pic_irq(void *opaque, int irq, int level)
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{
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DeviceState *dev = opaque;
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PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
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PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);
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qemu_set_irq(s->state.i8259[irq], level);
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}
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static void i82378_init(DeviceState *dev, I82378State *s)
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{
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ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
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ISADevice *pit;
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qemu_irq *out0_irq;
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/* This device has:
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2 82C59 (irq)
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1 82C54 (pit)
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2 82C37 (dma)
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NMI
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Utility Bus Support Registers
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All devices accept byte access only, except timer
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*/
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qdev_init_gpio_out(dev, s->out, 2);
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qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
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/* Workaround the fact that i8259 is not qdev'ified... */
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out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
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/* 2 82C59 (irq) */
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s->i8259 = i8259_init(isabus, *out0_irq);
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isa_bus_irqs(isabus, s->i8259);
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/* 1 82C54 (pit) */
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pit = pit_init(isabus, 0x40, 0);
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/* speaker */
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pcspk_init(pit);
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/* 2 82C37 (dma) */
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DMA_init(1, &s->out[1]);
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isa_create_simple(isabus, "i82374");
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/* timer */
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isa_create_simple(isabus, "mc146818rtc");
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}
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static int pci_i82378_init(PCIDevice *dev)
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{
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PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
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I82378State *s = &pci->state;
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uint8_t *pci_conf;
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pci_conf = dev->config;
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pci_set_word(pci_conf + PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pci_set_word(pci_conf + PCI_STATUS,
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
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memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
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pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
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memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
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memory_region_set_coalescing(&s->mem);
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pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
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/* Make I/O address read only */
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pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
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pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
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isa_mem_base = pci->isa_mem_base;
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isa_bus_new(&dev->qdev, pci_address_space_io(dev));
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i82378_init(&dev->qdev, s);
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return 0;
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}
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static Property i82378_properties[] = {
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DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
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DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
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DEFINE_PROP_END_OF_LIST()
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};
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static void pci_i82378_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = pci_i82378_init;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82378;
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k->revision = 0x03;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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k->subsystem_vendor_id = 0x0;
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k->subsystem_id = 0x0;
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dc->vmsd = &vmstate_pci_i82378;
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dc->props = i82378_properties;
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}
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static TypeInfo pci_i82378_info = {
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.name = "i82378",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIi82378State),
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.class_init = pci_i82378_class_init,
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};
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static void i82378_register_devices(void)
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{
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type_register_static(&pci_i82378_info);
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}
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device_init(i82378_register_devices)
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