qemu-e2k/target/ppc/translate
Matheus Ferst 8f0a4b6a9b target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The
Programming Environments Manual:

"For 32-bit implementations, the L field must be cleared, otherwise the
instruction form is invalid."

Some CPUs are known to deviate from this specification by ignoring the
L bit [1]. The stricter behavior, however, can help users that test
software with qemu, making it more likely to detect bugs that would
otherwise be silent.

If deemed necessary, a future patch can adapt this behavior based on
the specific CPU model.

[1] The 601 manual is the only one I've found that explicitly states
that the L bit is ignored, but we also observe this behavior in a 7447A
v1.2.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[dwg: Corrected whitespace error]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03 18:10:31 +10:00
..
dfp-impl.c.inc
dfp-ops.c.inc
fixedpoint-impl.c.inc target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree 2021-06-03 18:10:31 +10:00
fp-impl.c.inc
fp-ops.c.inc
spe-impl.c.inc
spe-ops.c.inc
vector-impl.c.inc target/ppc: Implement vcfuged instruction 2021-06-03 18:10:31 +10:00
vmx-impl.c.inc
vmx-ops.c.inc
vsx-impl.c.inc target/ppc: Fix load endianness for lxvwsx/lxvdsx 2021-05-19 10:44:04 +10:00
vsx-ops.c.inc ppc/translate: Implement lxvwsx opcode 2020-11-24 11:34:18 +11:00