084cfca143
This has been a tcg-specific function, but is also in use by hardware accelerators via physmem.c. This can cause link errors when tcg is disabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
/*
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* Flush the host cpu caches.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/cacheflush.h"
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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/* Caches are coherent and do not require flushing; symbol inline. */
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#elif defined(__mips__)
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#ifdef __OpenBSD__
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#include <machine/sysarch.h>
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#else
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#include <sys/cachectl.h>
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#endif
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void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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cacheflush((void *)start, stop - start, ICACHE);
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}
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#elif defined(__powerpc__)
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void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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uintptr_t p, start1, stop1;
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size_t dsize = qemu_dcache_linesize;
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size_t isize = qemu_icache_linesize;
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start1 = start & ~(dsize - 1);
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stop1 = (stop + dsize - 1) & ~(dsize - 1);
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for (p = start1; p < stop1; p += dsize) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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start &= start & ~(isize - 1);
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stop1 = (stop + isize - 1) & ~(isize - 1);
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for (p = start1; p < stop1; p += isize) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#elif defined(__sparc__)
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void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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uintptr_t p;
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for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
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__asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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}
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#else
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void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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__builtin___clear_cache((char *)start, (char *)stop);
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}
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#endif
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