273fef83f6
On non-P9 machines, the XIVE interrupt mode is not advertised, see spapr_dt_ov5_platform_support(). Add a couple of checks on the machine configuration to filter bogus setups and prevent OS failures : Interrupt modes CPU/Compat XICS XIVE dual P8/P8 OK QEMU failure (1) OK (3) P9/P8 OK QEMU failure (2) OK (3) P9/P9 OK OK OK (1) CPU exception model is incompatible with XIVE and the presenters will fail to realize. (2) CPU exception model is compatible with XIVE, but the XIVE CAS advertisement is dropped when in POWER8 mode. So we could ended up booting with the XIVE DT properties but without the HCALLs. Avoid confusing Linux with such settings and fail under QEMU. (3) force XICS in machine init Remove the check on XIVE-only machines in spapr_machine_init(), which has now become redundant. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190328100044.11408-1-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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.. | ||
e500-ccsr.h | ||
e500.c | ||
e500.h | ||
e500plat.c | ||
fdt.c | ||
Kconfig | ||
mac_newworld.c | ||
mac_oldworld.c | ||
mac.h | ||
Makefile.objs | ||
mpc8544_guts.c | ||
mpc8544ds.c | ||
pnv_bmc.c | ||
pnv_core.c | ||
pnv_lpc.c | ||
pnv_occ.c | ||
pnv_psi.c | ||
pnv_xscom.c | ||
pnv.c | ||
ppc4xx_devs.c | ||
ppc4xx_pci.c | ||
ppc405_boards.c | ||
ppc405_uc.c | ||
ppc405.h | ||
ppc440_bamboo.c | ||
ppc440_pcix.c | ||
ppc440_uc.c | ||
ppc440.h | ||
ppc_booke.c | ||
ppc.c | ||
ppce500_spin.c | ||
prep_systemio.c | ||
prep.c | ||
rs6000_mc.c | ||
sam460ex.c | ||
spapr_caps.c | ||
spapr_cpu_core.c | ||
spapr_drc.c | ||
spapr_events.c | ||
spapr_hcall.c | ||
spapr_iommu.c | ||
spapr_irq.c | ||
spapr_ovec.c | ||
spapr_pci_vfio.c | ||
spapr_pci.c | ||
spapr_rng.c | ||
spapr_rtas_ddw.c | ||
spapr_rtas.c | ||
spapr_rtc.c | ||
spapr_vio.c | ||
spapr.c | ||
trace-events | ||
virtex_ml507.c |