103db49a10
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-7-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
212 lines
6.5 KiB
C
212 lines
6.5 KiB
C
/*
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* Emulation of Allwinner EMAC Fast Ethernet controller and
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* Realtek RTL8201CP PHY
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* Allwinner EMAC register definitions from Linux kernel are:
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* Copyright 2012 Stefan Roese <sr@denx.de>
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* Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
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* Copyright 1997 Sten Wang
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef AW_EMAC_H
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#define AW_EMAC_H
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#include "net/net.h"
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#include "qemu/fifo8.h"
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#define TYPE_AW_EMAC "allwinner-emac"
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#define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
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/*
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* Allwinner EMAC register list
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*/
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#define EMAC_CTL_REG 0x00
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#define EMAC_TX_MODE_REG 0x04
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#define EMAC_TX_FLOW_REG 0x08
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#define EMAC_TX_CTL0_REG 0x0C
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#define EMAC_TX_CTL1_REG 0x10
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#define EMAC_TX_INS_REG 0x14
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#define EMAC_TX_PL0_REG 0x18
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#define EMAC_TX_PL1_REG 0x1C
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#define EMAC_TX_STA_REG 0x20
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#define EMAC_TX_IO_DATA_REG 0x24
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#define EMAC_TX_IO_DATA1_REG 0x28
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#define EMAC_TX_TSVL0_REG 0x2C
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#define EMAC_TX_TSVH0_REG 0x30
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#define EMAC_TX_TSVL1_REG 0x34
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#define EMAC_TX_TSVH1_REG 0x38
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#define EMAC_RX_CTL_REG 0x3C
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#define EMAC_RX_HASH0_REG 0x40
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#define EMAC_RX_HASH1_REG 0x44
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#define EMAC_RX_STA_REG 0x48
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#define EMAC_RX_IO_DATA_REG 0x4C
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#define EMAC_RX_FBC_REG 0x50
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#define EMAC_INT_CTL_REG 0x54
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#define EMAC_INT_STA_REG 0x58
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#define EMAC_MAC_CTL0_REG 0x5C
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#define EMAC_MAC_CTL1_REG 0x60
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#define EMAC_MAC_IPGT_REG 0x64
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#define EMAC_MAC_IPGR_REG 0x68
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#define EMAC_MAC_CLRT_REG 0x6C
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#define EMAC_MAC_MAXF_REG 0x70
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#define EMAC_MAC_SUPP_REG 0x74
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#define EMAC_MAC_TEST_REG 0x78
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#define EMAC_MAC_MCFG_REG 0x7C
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#define EMAC_MAC_MCMD_REG 0x80
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#define EMAC_MAC_MADR_REG 0x84
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#define EMAC_MAC_MWTD_REG 0x88
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#define EMAC_MAC_MRDD_REG 0x8C
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#define EMAC_MAC_MIND_REG 0x90
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#define EMAC_MAC_SSRR_REG 0x94
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#define EMAC_MAC_A0_REG 0x98
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#define EMAC_MAC_A1_REG 0x9C
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#define EMAC_MAC_A2_REG 0xA0
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#define EMAC_SAFX_L_REG0 0xA4
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#define EMAC_SAFX_H_REG0 0xA8
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#define EMAC_SAFX_L_REG1 0xAC
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#define EMAC_SAFX_H_REG1 0xB0
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#define EMAC_SAFX_L_REG2 0xB4
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#define EMAC_SAFX_H_REG2 0xB8
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#define EMAC_SAFX_L_REG3 0xBC
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#define EMAC_SAFX_H_REG3 0xC0
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/* CTL register fields */
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#define EMAC_CTL_RESET (1 << 0)
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#define EMAC_CTL_TX_EN (1 << 1)
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#define EMAC_CTL_RX_EN (1 << 2)
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/* TX MODE register fields */
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#define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0)
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#define EMAC_TX_MODE_DMA_EN (1 << 1)
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/* RX CTL register fields */
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#define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1)
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#define EMAC_RX_CTL_DMA_EN (1 << 2)
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#define EMAC_RX_CTL_PASS_ALL_EN (1 << 4)
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#define EMAC_RX_CTL_PASS_CTL_EN (1 << 5)
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#define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6)
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#define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7)
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#define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8)
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#define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16)
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#define EMAC_RX_CTL_DA_FILTER_EN (1 << 17)
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#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20)
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#define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21)
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#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22)
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#define EMAC_RX_CTL_SA_FILTER_EN (1 << 24)
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#define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25)
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/* RX IO DATA register fields */
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#define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16))
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#define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4)
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#define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5)
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#define EMAC_RX_IO_DATA_STATUS_OK (1 << 7)
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#define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */
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/* PHY registers */
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#define MII_BMCR 0
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#define MII_BMSR 1
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#define MII_PHYID1 2
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#define MII_PHYID2 3
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#define MII_ANAR 4
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#define MII_ANLPAR 5
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#define MII_ANER 6
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#define MII_NSR 16
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#define MII_LBREMR 17
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#define MII_REC 18
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#define MII_SNRDR 19
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#define MII_TEST 25
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/* PHY registers fields */
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#define MII_BMCR_RESET (1 << 15)
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#define MII_BMCR_LOOPBACK (1 << 14)
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#define MII_BMCR_SPEED (1 << 13)
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#define MII_BMCR_AUTOEN (1 << 12)
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#define MII_BMCR_FD (1 << 8)
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#define MII_BMSR_100TX_FD (1 << 14)
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#define MII_BMSR_100TX_HD (1 << 13)
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#define MII_BMSR_10T_FD (1 << 12)
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#define MII_BMSR_10T_HD (1 << 11)
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#define MII_BMSR_MFPS (1 << 6)
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#define MII_BMSR_AN_COMP (1 << 5)
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#define MII_BMSR_AUTONEG (1 << 3)
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#define MII_BMSR_LINK_ST (1 << 2)
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#define MII_ANAR_TXFD (1 << 8)
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#define MII_ANAR_TX (1 << 7)
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#define MII_ANAR_10FD (1 << 6)
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#define MII_ANAR_10 (1 << 5)
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#define MII_ANAR_CSMACD (1 << 0)
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#define RTL8201CP_PHYID1 0x0000
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#define RTL8201CP_PHYID2 0x8201
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/* INT CTL and INT STA registers fields */
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#define EMAC_INT_TX_CHAN(x) (1 << (x))
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#define EMAC_INT_RX (1 << 8)
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/* Due to lack of specifications, size of fifos is chosen arbitrarily */
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#define TX_FIFO_SIZE (4 * 1024)
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#define RX_FIFO_SIZE (32 * 1024)
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#define NUM_TX_FIFOS 2
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#define RX_HDR_SIZE 8
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#define CRC_SIZE 4
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#define PHY_REG_SHIFT 0
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#define PHY_ADDR_SHIFT 8
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typedef struct RTL8201CPState {
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uint16_t bmcr;
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uint16_t bmsr;
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uint16_t anar;
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uint16_t anlpar;
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} RTL8201CPState;
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typedef struct AwEmacState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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RTL8201CPState mii;
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uint8_t phy_addr;
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uint32_t ctl;
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uint32_t tx_mode;
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uint32_t rx_ctl;
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uint32_t int_ctl;
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uint32_t int_sta;
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uint32_t phy_target;
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Fifo8 rx_fifo;
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uint32_t rx_num_packets;
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uint32_t rx_packet_size;
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uint32_t rx_packet_pos;
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Fifo8 tx_fifo[NUM_TX_FIFOS];
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uint32_t tx_length[NUM_TX_FIFOS];
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uint32_t tx_channel;
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} AwEmacState;
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#endif
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