92371bd903
Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
806 lines
24 KiB
C
806 lines
24 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/qemu-print.h"
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#include "qemu/ctype.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/exec-all.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "fpu/softfloat-helpers.h"
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/* RISC-V CPU definitions */
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static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
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const char * const riscv_int_regnames[] = {
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"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
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"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
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"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
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"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
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"x28/t3", "x29/t4", "x30/t5", "x31/t6"
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};
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const char * const riscv_fpr_regnames[] = {
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"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
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"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
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"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
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"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
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"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
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"f30/ft10", "f31/ft11"
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};
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static const char * const riscv_excp_names[] = {
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"misaligned_fetch",
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"fault_fetch",
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"illegal_instruction",
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"breakpoint",
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"misaligned_load",
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"fault_load",
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"misaligned_store",
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"fault_store",
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"user_ecall",
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"supervisor_ecall",
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"hypervisor_ecall",
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"machine_ecall",
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"exec_page_fault",
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"load_page_fault",
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"reserved",
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"store_page_fault",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"guest_exec_page_fault",
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"guest_load_page_fault",
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"reserved",
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"guest_store_page_fault",
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};
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static const char * const riscv_intr_names[] = {
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"u_software",
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"s_software",
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"vs_software",
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"m_software",
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"u_timer",
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"s_timer",
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"vs_timer",
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"m_timer",
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"u_external",
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"s_external",
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"vs_external",
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"m_external",
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"reserved",
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"reserved",
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"reserved",
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"reserved"
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};
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const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
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{
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if (async) {
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return (cause < ARRAY_SIZE(riscv_intr_names)) ?
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riscv_intr_names[cause] : "(unknown)";
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} else {
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return (cause < ARRAY_SIZE(riscv_excp_names)) ?
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riscv_excp_names[cause] : "(unknown)";
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}
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}
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static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
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{
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env->misa_mxl_max = env->misa_mxl = mxl;
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env->misa_ext_mask = env->misa_ext = ext;
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}
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static void set_priv_version(CPURISCVState *env, int priv_ver)
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{
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env->priv_ver = priv_ver;
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}
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static void set_vext_version(CPURISCVState *env, int vext_ver)
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{
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env->vext_ver = vext_ver;
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}
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static void set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
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{
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#ifndef CONFIG_USER_ONLY
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env->resetvec = resetvec;
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#endif
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}
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static void riscv_any_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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#if defined(TARGET_RISCV32)
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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#elif defined(TARGET_RISCV64)
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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#endif
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set_priv_version(env, PRIV_VERSION_1_11_0);
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}
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#if defined(TARGET_RISCV64)
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static void rv64_base_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, MXL_RV64, 0);
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}
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static void rv64_sifive_u_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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}
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static void rv64_sifive_e_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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#else
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static void rv32_base_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, MXL_RV32, 0);
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}
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static void rv32_sifive_u_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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}
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static void rv32_sifive_e_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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static void rv32_ibex_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
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}
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static void rv32_imafcu_nommu_cpu_init(Object *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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qdev_prop_set_bit(DEVICE(obj), "mmu", false);
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}
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#endif
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static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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char **cpuname;
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cpuname = g_strsplit(cpu_model, ",", 1);
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typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
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oc = object_class_by_name(typename);
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g_strfreev(cpuname);
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g_free(typename);
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if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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int i;
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#if !defined(CONFIG_USER_ONLY)
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env));
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}
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#endif
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc);
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#ifndef CONFIG_USER_ONLY
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
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(target_ulong)(env->mstatus >> 32));
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}
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
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(target_ulong)env->vsstatus);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
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if (riscv_has_ext(env, RVH)) {
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
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qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
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#endif
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
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riscv_int_regnames[i], env->gpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 32; i++) {
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qemu_fprintf(f, " %-8s %016" PRIx64,
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riscv_fpr_regnames[i], env->fpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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}
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}
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static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = value;
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = tb->pc;
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}
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static bool riscv_cpu_has_work(CPUState *cs)
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{
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#ifndef CONFIG_USER_ONLY
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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/*
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* Definition of the WFI instruction requires it to ignore the privilege
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* mode and delegation registers, but respect individual enables
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*/
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return (env->mip & env->mie) != 0;
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#else
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return true;
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#endif
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}
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void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->pc = data[0];
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}
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static void riscv_cpu_reset(DeviceState *dev)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(cs);
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
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CPURISCVState *env = &cpu->env;
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mcc->parent_reset(dev);
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#ifndef CONFIG_USER_ONLY
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env->misa_mxl = env->misa_mxl_max;
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env->priv = PRV_M;
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env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
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if (env->misa_mxl > MXL_RV32) {
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/*
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* The reset status of SXL/UXL is undefined, but mstatus is WARL
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* and we must ensure that the value after init is valid for read.
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*/
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env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
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env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
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}
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env->mcause = 0;
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env->pc = env->resetvec;
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env->two_stage_lookup = false;
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#endif
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cs->exception_index = RISCV_EXCP_NONE;
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env->load_res = -1;
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set_default_nan_mode(1, &env->fp_status);
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}
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static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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{
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RISCVCPU *cpu = RISCV_CPU(s);
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switch (riscv_cpu_mxl(&cpu->env)) {
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case MXL_RV32:
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info->print_insn = print_insn_riscv32;
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break;
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case MXL_RV64:
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info->print_insn = print_insn_riscv64;
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(dev);
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CPURISCVState *env = &cpu->env;
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
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int priv_version = 0;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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if (cpu->cfg.priv_spec) {
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if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
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priv_version = PRIV_VERSION_1_11_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
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priv_version = PRIV_VERSION_1_10_0;
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} else {
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error_setg(errp,
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"Unsupported privilege spec version '%s'",
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cpu->cfg.priv_spec);
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return;
|
|
}
|
|
}
|
|
|
|
if (priv_version) {
|
|
set_priv_version(env, priv_version);
|
|
} else if (!env->priv_ver) {
|
|
set_priv_version(env, PRIV_VERSION_1_11_0);
|
|
}
|
|
|
|
if (cpu->cfg.mmu) {
|
|
set_feature(env, RISCV_FEATURE_MMU);
|
|
}
|
|
|
|
if (cpu->cfg.pmp) {
|
|
set_feature(env, RISCV_FEATURE_PMP);
|
|
|
|
/*
|
|
* Enhanced PMP should only be available
|
|
* on harts with PMP support
|
|
*/
|
|
if (cpu->cfg.epmp) {
|
|
set_feature(env, RISCV_FEATURE_EPMP);
|
|
}
|
|
}
|
|
|
|
set_resetvec(env, cpu->cfg.resetvec);
|
|
|
|
/* Validate that MISA_MXL is set properly. */
|
|
switch (env->misa_mxl_max) {
|
|
#ifdef TARGET_RISCV64
|
|
case MXL_RV64:
|
|
break;
|
|
#endif
|
|
case MXL_RV32:
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
assert(env->misa_mxl_max == env->misa_mxl);
|
|
|
|
/* If only MISA_EXT is unset for misa, then set it from properties */
|
|
if (env->misa_ext == 0) {
|
|
uint32_t ext = 0;
|
|
|
|
/* Do some ISA extension error checking */
|
|
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
|
|
error_setg(errp,
|
|
"I and E extensions are incompatible");
|
|
return;
|
|
}
|
|
|
|
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
|
|
error_setg(errp,
|
|
"Either I or E extension must be set");
|
|
return;
|
|
}
|
|
|
|
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
|
|
cpu->cfg.ext_a & cpu->cfg.ext_f &
|
|
cpu->cfg.ext_d)) {
|
|
warn_report("Setting G will also set IMAFD");
|
|
cpu->cfg.ext_i = true;
|
|
cpu->cfg.ext_m = true;
|
|
cpu->cfg.ext_a = true;
|
|
cpu->cfg.ext_f = true;
|
|
cpu->cfg.ext_d = true;
|
|
}
|
|
|
|
/* Set the ISA extensions, checks should have happened above */
|
|
if (cpu->cfg.ext_i) {
|
|
ext |= RVI;
|
|
}
|
|
if (cpu->cfg.ext_e) {
|
|
ext |= RVE;
|
|
}
|
|
if (cpu->cfg.ext_m) {
|
|
ext |= RVM;
|
|
}
|
|
if (cpu->cfg.ext_a) {
|
|
ext |= RVA;
|
|
}
|
|
if (cpu->cfg.ext_f) {
|
|
ext |= RVF;
|
|
}
|
|
if (cpu->cfg.ext_d) {
|
|
ext |= RVD;
|
|
}
|
|
if (cpu->cfg.ext_c) {
|
|
ext |= RVC;
|
|
}
|
|
if (cpu->cfg.ext_s) {
|
|
ext |= RVS;
|
|
}
|
|
if (cpu->cfg.ext_u) {
|
|
ext |= RVU;
|
|
}
|
|
if (cpu->cfg.ext_h) {
|
|
ext |= RVH;
|
|
}
|
|
if (cpu->cfg.ext_v) {
|
|
int vext_version = VEXT_VERSION_0_07_1;
|
|
ext |= RVV;
|
|
if (!is_power_of_2(cpu->cfg.vlen)) {
|
|
error_setg(errp,
|
|
"Vector extension VLEN must be power of 2");
|
|
return;
|
|
}
|
|
if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
|
|
error_setg(errp,
|
|
"Vector extension implementation only supports VLEN "
|
|
"in the range [128, %d]", RV_VLEN_MAX);
|
|
return;
|
|
}
|
|
if (!is_power_of_2(cpu->cfg.elen)) {
|
|
error_setg(errp,
|
|
"Vector extension ELEN must be power of 2");
|
|
return;
|
|
}
|
|
if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
|
|
error_setg(errp,
|
|
"Vector extension implementation only supports ELEN "
|
|
"in the range [8, 64]");
|
|
return;
|
|
}
|
|
if (cpu->cfg.vext_spec) {
|
|
if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
|
|
vext_version = VEXT_VERSION_0_07_1;
|
|
} else {
|
|
error_setg(errp,
|
|
"Unsupported vector spec version '%s'",
|
|
cpu->cfg.vext_spec);
|
|
return;
|
|
}
|
|
} else {
|
|
qemu_log("vector version is not specified, "
|
|
"use the default value v0.7.1\n");
|
|
}
|
|
set_vext_version(env, vext_version);
|
|
}
|
|
|
|
set_misa(env, env->misa_mxl, ext);
|
|
}
|
|
|
|
riscv_cpu_register_gdb_regs_for_features(cs);
|
|
|
|
qemu_init_vcpu(cs);
|
|
cpu_reset(cs);
|
|
|
|
mcc->parent_realize(dev, errp);
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
static void riscv_cpu_set_irq(void *opaque, int irq, int level)
|
|
{
|
|
RISCVCPU *cpu = RISCV_CPU(opaque);
|
|
|
|
switch (irq) {
|
|
case IRQ_U_SOFT:
|
|
case IRQ_S_SOFT:
|
|
case IRQ_VS_SOFT:
|
|
case IRQ_M_SOFT:
|
|
case IRQ_U_TIMER:
|
|
case IRQ_S_TIMER:
|
|
case IRQ_VS_TIMER:
|
|
case IRQ_M_TIMER:
|
|
case IRQ_U_EXT:
|
|
case IRQ_S_EXT:
|
|
case IRQ_VS_EXT:
|
|
case IRQ_M_EXT:
|
|
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
static void riscv_cpu_init(Object *obj)
|
|
{
|
|
RISCVCPU *cpu = RISCV_CPU(obj);
|
|
|
|
cpu_set_cpustate_pointers(cpu);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
|
|
#endif /* CONFIG_USER_ONLY */
|
|
}
|
|
|
|
static Property riscv_cpu_properties[] = {
|
|
/* Defaults for standard extensions */
|
|
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
|
|
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
|
|
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
|
|
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
|
|
DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
|
|
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
|
|
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
|
|
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
|
|
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
|
|
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
|
|
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
|
|
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
|
|
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
|
|
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
|
|
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
|
|
|
|
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
|
|
|
|
/* These are experimental so mark with 'x-' */
|
|
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
|
|
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
|
|
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
|
|
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
|
|
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
|
|
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
|
|
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
|
|
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
|
|
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
|
|
/* ePMP 0.9.3 */
|
|
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
|
|
|
|
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static gchar *riscv_gdb_arch_name(CPUState *cs)
|
|
{
|
|
RISCVCPU *cpu = RISCV_CPU(cs);
|
|
CPURISCVState *env = &cpu->env;
|
|
|
|
switch (riscv_cpu_mxl(env)) {
|
|
case MXL_RV32:
|
|
return g_strdup("riscv:rv32");
|
|
case MXL_RV64:
|
|
return g_strdup("riscv:rv64");
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
|
|
{
|
|
RISCVCPU *cpu = RISCV_CPU(cs);
|
|
|
|
if (strcmp(xmlname, "riscv-csr.xml") == 0) {
|
|
return cpu->dyn_csr_xml;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
#include "hw/core/sysemu-cpu-ops.h"
|
|
|
|
static const struct SysemuCPUOps riscv_sysemu_ops = {
|
|
.get_phys_page_debug = riscv_cpu_get_phys_page_debug,
|
|
.write_elf64_note = riscv_cpu_write_elf64_note,
|
|
.write_elf32_note = riscv_cpu_write_elf32_note,
|
|
.legacy_vmsd = &vmstate_riscv_cpu,
|
|
};
|
|
#endif
|
|
|
|
#include "hw/core/tcg-cpu-ops.h"
|
|
|
|
static const struct TCGCPUOps riscv_tcg_ops = {
|
|
.initialize = riscv_translate_init,
|
|
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
|
|
.tlb_fill = riscv_cpu_tlb_fill,
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
|
|
.do_interrupt = riscv_cpu_do_interrupt,
|
|
.do_transaction_failed = riscv_cpu_do_transaction_failed,
|
|
.do_unaligned_access = riscv_cpu_do_unaligned_access,
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
};
|
|
|
|
static void riscv_cpu_class_init(ObjectClass *c, void *data)
|
|
{
|
|
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
|
|
CPUClass *cc = CPU_CLASS(c);
|
|
DeviceClass *dc = DEVICE_CLASS(c);
|
|
|
|
device_class_set_parent_realize(dc, riscv_cpu_realize,
|
|
&mcc->parent_realize);
|
|
|
|
device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
|
|
|
|
cc->class_by_name = riscv_cpu_class_by_name;
|
|
cc->has_work = riscv_cpu_has_work;
|
|
cc->dump_state = riscv_cpu_dump_state;
|
|
cc->set_pc = riscv_cpu_set_pc;
|
|
cc->gdb_read_register = riscv_cpu_gdb_read_register;
|
|
cc->gdb_write_register = riscv_cpu_gdb_write_register;
|
|
cc->gdb_num_core_regs = 33;
|
|
#if defined(TARGET_RISCV32)
|
|
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
|
|
#elif defined(TARGET_RISCV64)
|
|
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
|
|
#endif
|
|
cc->gdb_stop_before_watchpoint = true;
|
|
cc->disas_set_info = riscv_cpu_disas_set_info;
|
|
#ifndef CONFIG_USER_ONLY
|
|
cc->sysemu_ops = &riscv_sysemu_ops;
|
|
#endif
|
|
cc->gdb_arch_name = riscv_gdb_arch_name;
|
|
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
|
|
cc->tcg_ops = &riscv_tcg_ops;
|
|
|
|
device_class_set_props(dc, riscv_cpu_properties);
|
|
}
|
|
|
|
char *riscv_isa_string(RISCVCPU *cpu)
|
|
{
|
|
int i;
|
|
const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
|
|
char *isa_str = g_new(char, maxlen);
|
|
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
|
|
for (i = 0; i < sizeof(riscv_exts); i++) {
|
|
if (cpu->env.misa_ext & RV(riscv_exts[i])) {
|
|
*p++ = qemu_tolower(riscv_exts[i]);
|
|
}
|
|
}
|
|
*p = '\0';
|
|
return isa_str;
|
|
}
|
|
|
|
static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
|
|
{
|
|
ObjectClass *class_a = (ObjectClass *)a;
|
|
ObjectClass *class_b = (ObjectClass *)b;
|
|
const char *name_a, *name_b;
|
|
|
|
name_a = object_class_get_name(class_a);
|
|
name_b = object_class_get_name(class_b);
|
|
return strcmp(name_a, name_b);
|
|
}
|
|
|
|
static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
|
|
{
|
|
const char *typename = object_class_get_name(OBJECT_CLASS(data));
|
|
int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
|
|
|
|
qemu_printf("%.*s\n", len, typename);
|
|
}
|
|
|
|
void riscv_cpu_list(void)
|
|
{
|
|
GSList *list;
|
|
|
|
list = object_class_get_list(TYPE_RISCV_CPU, false);
|
|
list = g_slist_sort(list, riscv_cpu_list_compare);
|
|
g_slist_foreach(list, riscv_cpu_list_entry, NULL);
|
|
g_slist_free(list);
|
|
}
|
|
|
|
#define DEFINE_CPU(type_name, initfn) \
|
|
{ \
|
|
.name = type_name, \
|
|
.parent = TYPE_RISCV_CPU, \
|
|
.instance_init = initfn \
|
|
}
|
|
|
|
static const TypeInfo riscv_cpu_type_infos[] = {
|
|
{
|
|
.name = TYPE_RISCV_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(RISCVCPU),
|
|
.instance_align = __alignof__(RISCVCPU),
|
|
.instance_init = riscv_cpu_init,
|
|
.abstract = true,
|
|
.class_size = sizeof(RISCVCPUClass),
|
|
.class_init = riscv_cpu_class_init,
|
|
},
|
|
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
|
|
#if defined(TARGET_RISCV32)
|
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
|
|
#elif defined(TARGET_RISCV64)
|
|
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
|
|
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
|
|
#endif
|
|
};
|
|
|
|
DEFINE_TYPES(riscv_cpu_type_infos)
|