507 lines
16 KiB
C
507 lines
16 KiB
C
/*
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* ARM gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "internals.h"
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#include "cpregs.h"
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typedef struct RegisterSysregXmlParam {
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CPUState *cs;
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GString *s;
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int n;
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} RegisterSysregXmlParam;
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/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
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whatever the target description contains. Due to a historical mishap
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the FPA registers appear in between core integer regs and the CPSR.
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We hack round this by giving the FPA regs zero size when talking to a
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newer gdb. */
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int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 16) {
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/* Core integer register. */
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return gdb_get_reg32(mem_buf, env->regs[n]);
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}
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if (n < 24) {
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/* FPA registers. */
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if (gdb_has_xml) {
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return 0;
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}
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return gdb_get_zeroes(mem_buf, 12);
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}
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switch (n) {
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case 24:
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/* FPA status register. */
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if (gdb_has_xml) {
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return 0;
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}
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return gdb_get_reg32(mem_buf, 0);
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case 25:
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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return gdb_get_reg32(mem_buf, xpsr_read(env));
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} else {
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return gdb_get_reg32(mem_buf, cpsr_read(env));
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}
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}
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/* Unknown register. */
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return 0;
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}
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int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t tmp;
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tmp = ldl_p(mem_buf);
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/*
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* Mask out low bits of PC to workaround gdb bugs.
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* This avoids an assert in thumb_tr_translate_insn, because it is
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* architecturally impossible to misalign the pc.
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* This will probably cause problems if we ever implement the
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* Jazelle DBX extensions.
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*/
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if (n == 15) {
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tmp &= ~1;
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}
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if (n < 16) {
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/* Core integer register. */
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if (n == 13 && arm_feature(env, ARM_FEATURE_M)) {
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/* M profile SP low bits are always 0 */
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tmp &= ~3;
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}
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env->regs[n] = tmp;
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return 4;
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}
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if (n < 24) { /* 16-23 */
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/* FPA registers (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 12;
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}
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switch (n) {
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case 24:
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/* FPA status register (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 4;
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case 25:
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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/*
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* Don't allow writing to XPSR.Exception as it can cause
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* a transition into or out of handler mode (it's not
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* writable via the MSR insn so this is a reasonable
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* restriction). Other fields are safe to update.
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*/
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xpsr_write(env, tmp, ~XPSR_EXCP);
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} else {
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cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
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}
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = env_archcpu(env);
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int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
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/* VFP data registers are always little-endian. */
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if (reg < nregs) {
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return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
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}
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if (arm_feature(env, ARM_FEATURE_NEON)) {
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/* Aliases for Q regs. */
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nregs += 16;
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if (reg < nregs) {
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uint64_t *q = aa32_vfp_qreg(env, reg - 32);
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return gdb_get_reg128(buf, q[0], q[1]);
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}
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}
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switch (reg - nregs) {
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case 0:
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return gdb_get_reg32(buf, vfp_get_fpscr(env));
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}
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return 0;
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}
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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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ARMCPU *cpu = env_archcpu(env);
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int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
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if (reg < nregs) {
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*aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
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return 8;
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}
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if (arm_feature(env, ARM_FEATURE_NEON)) {
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nregs += 16;
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if (reg < nregs) {
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uint64_t *q = aa32_vfp_qreg(env, reg - 32);
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q[0] = ldq_le_p(buf);
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q[1] = ldq_le_p(buf + 8);
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return 16;
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}
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}
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switch (reg - nregs) {
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case 0:
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vfp_set_fpscr(env, ldl_p(buf));
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return 4;
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}
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return 0;
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}
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static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
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{
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switch (reg) {
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case 0:
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return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
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case 1:
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return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
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}
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return 0;
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}
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static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
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{
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switch (reg) {
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case 0:
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env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
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return 4;
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case 1:
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env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
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return 4;
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}
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return 0;
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}
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static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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switch (reg) {
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case 0:
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return gdb_get_reg32(buf, env->v7m.vpr);
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default:
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return 0;
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}
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}
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static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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switch (reg) {
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case 0:
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env->v7m.vpr = ldl_p(buf);
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return 4;
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default:
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return 0;
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}
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}
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/**
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* arm_get/set_gdb_*: get/set a gdb register
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* @env: the CPU state
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* @buf: a buffer to copy to/from
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* @reg: register number (offset from start of group)
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*
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* We return the number of bytes copied
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*/
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static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = env_archcpu(env);
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const ARMCPRegInfo *ri;
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uint32_t key;
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key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
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ri = get_arm_cp_reginfo(cpu->cp_regs, key);
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if (ri) {
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if (cpreg_field_is_64bit(ri)) {
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return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
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} else {
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return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
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}
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}
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return 0;
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}
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static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
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{
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return 0;
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}
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static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
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ARMCPRegInfo *ri, uint32_t ri_key,
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int bitsize, int regnum)
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{
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g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
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g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
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g_string_append_printf(s, " regnum=\"%d\"", regnum);
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g_string_append_printf(s, " group=\"cp_regs\"/>");
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dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
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dyn_xml->num++;
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}
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static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
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gpointer p)
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{
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uint32_t ri_key = (uintptr_t)key;
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ARMCPRegInfo *ri = value;
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RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
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GString *s = param->s;
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ARMCPU *cpu = ARM_CPU(param->cs);
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CPUARMState *env = &cpu->env;
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DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
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if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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if (ri->state == ARM_CP_STATE_AA64) {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
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param->n++);
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}
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} else {
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if (ri->state == ARM_CP_STATE_AA32) {
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if (!arm_feature(env, ARM_FEATURE_EL3) &&
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(ri->secure & ARM_CP_SECSTATE_S)) {
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return;
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}
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if (ri->type & ARM_CP_64BIT) {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
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param->n++);
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} else {
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arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
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param->n++);
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}
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}
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}
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}
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}
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int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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RegisterSysregXmlParam param = {cs, s, base_reg};
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cpu->dyn_sysreg_xml.num = 0;
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cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
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g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m);
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g_string_append_printf(s, "</feature>");
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cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
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return cpu->dyn_sysreg_xml.num;
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}
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struct TypeSize {
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const char *gdb_type;
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int size;
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const char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "ieee_double", 64, 'd', 'f' },
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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/* 32 bit */
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{ "ieee_single", 32, 's', 'f' },
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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/* 16 bit */
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{ "ieee_half", 16, 'h', 'f' },
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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g_autoptr(GString) ts = g_string_new("");
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int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
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info->num = 0;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
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g_string_append_printf(s,
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"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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ts->str, vec_lanes[i].gdb_type, count);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
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for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
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if (vec_lanes[j].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
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vec_lanes[j].suffix,
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vec_lanes[j].sz, vec_lanes[j].suffix);
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}
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}
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g_string_append(s, "</union>");
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}
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/* And now the final union of unions */
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g_string_append(s, "<union id=\"svev\">");
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
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suf[i], suf[i]);
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}
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g_string_append(s, "</union>");
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/* Finally the sve prefix type */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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reg_width / 8);
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/* Then define each register in parts for each vq */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svev\"/>",
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i, reg_width, base_reg++);
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info->num++;
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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info->num += 2;
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svep\"/>",
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i, cpu->sve_max_vq * 16, base_reg++);
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info->num++;
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"svep\"/>",
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cpu->sve_max_vq * 16, base_reg++);
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" type=\"int\"/>",
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base_reg++);
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info->num += 2;
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g_string_append_printf(s, "</feature>");
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cpu->dyn_svereg_xml.desc = g_string_free(s, false);
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return cpu->dyn_svereg_xml.num;
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}
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const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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if (strcmp(xmlname, "system-registers.xml") == 0) {
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return cpu->dyn_sysreg_xml.desc;
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} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
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return cpu->dyn_svereg_xml.desc;
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}
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return NULL;
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}
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUARMState *env = &cpu->env;
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/*
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* The lower part of each SVE register aliases to the FPU
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* registers so we don't need to include both.
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*/
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#ifdef TARGET_AARCH64
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if (isar_feature_aa64_sve(&cpu->isar)) {
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gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
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arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
|
|
"sve-registers.xml", 0);
|
|
} else {
|
|
gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
|
|
aarch64_fpu_gdb_set_reg,
|
|
34, "aarch64-fpu.xml", 0);
|
|
}
|
|
#endif
|
|
} else {
|
|
if (arm_feature(env, ARM_FEATURE_NEON)) {
|
|
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
|
|
49, "arm-neon.xml", 0);
|
|
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
|
|
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
|
|
33, "arm-vfp3.xml", 0);
|
|
} else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
|
|
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
|
|
17, "arm-vfp.xml", 0);
|
|
}
|
|
if (!arm_feature(env, ARM_FEATURE_M)) {
|
|
/*
|
|
* A and R profile have FP sysregs FPEXC and FPSID that we
|
|
* expose to gdb.
|
|
*/
|
|
gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
|
|
2, "arm-vfp-sysregs.xml", 0);
|
|
}
|
|
}
|
|
if (cpu_isar_feature(aa32_mve, cpu)) {
|
|
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
|
|
1, "arm-m-profile-mve.xml", 0);
|
|
}
|
|
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
|
|
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
|
|
"system-registers.xml", 0);
|
|
|
|
}
|