OpenE2K/qemu-e2k
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qemu-e2k/include/hw/riscv
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Alistair Francis a8259b5323 riscv: Pass RISCVHartArrayState by pointer 
We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.

Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
2021-01-16 14:34:46 -08:00
..
boot_opensbi.h
…
boot.h
riscv: Pass RISCVHartArrayState by pointer
2021-01-16 14:34:46 -08:00
microchip_pfsoc.h
hw/riscv: microchip_pfsoc: add QSPI NOR flash
2020-12-17 21:56:43 -08:00
numa.h
…
opentitan.h
riscv/opentitan: Update the OpenTitan memory layout
2020-12-17 21:56:44 -08:00
riscv_hart.h
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
sifive_cpu.h
…
sifive_e.h
sifive_e: Rename memmap enum constants
2020-09-18 13:49:48 -04:00
sifive_u.h
hw/riscv: sifive_u: Allow specifying the CPU
2020-10-22 12:00:22 -07:00
spike.h
riscv: spike: Remove target macro conditionals
2020-12-17 21:56:44 -08:00
virt.h
riscv: virt: Remove target macro conditionals
2020-12-17 21:56:44 -08:00