qemu-e2k/target/riscv/insn_trans/trans_xventanacondops.c.inc
Philipp Tomsich 4f2493146d target/riscv: redirect XVentanaCondOps to use the Zicond functions
The Zicond standard extension implements the same instruction
semantics as XVentanaCondOps, although using different mnemonics and
opcodes.

Point XVentanaCondOps to the (newly implemented) Zicond implementation
to reduce the future maintenance burden.

Also updating MAINTAINERS as trans_xventanacondops.c.inc.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05 10:49:50 +10:00

28 lines
933 B
C++

/*
* RISC-V translation routines for the XVentanaCondOps extension.
*
* Copyright (c) 2021-2023 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
{
return gen_logic(ctx, a, gen_czero_eqz);
}
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
{
return gen_logic(ctx, a, gen_czero_nez);
}