eae6bcbfd8
Also zero pci_irq_levels on reset to avoid stuck irq after reset.
Based on 15a1956af9 by Gleb Natapov.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
375 lines
11 KiB
C
375 lines
11 KiB
C
/*
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* QEMU i440FX/PIIX3 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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typedef PCIHostState I440FXState;
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static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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I440FXState *s = opaque;
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s->config_reg = val;
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}
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static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
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{
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I440FXState *s = opaque;
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return s->config_reg;
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}
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static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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{
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int slot_addend;
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slot_addend = (pci_dev->devfn >> 3) - 1;
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return (irq_num + slot_addend) & 3;
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}
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static target_phys_addr_t isa_page_descs[384 / 4];
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static uint8_t smm_enabled;
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static int pci_irq_levels[4];
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static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
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{
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uint32_t addr;
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// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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switch(r) {
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case 3:
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/* RAM */
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cpu_register_physical_memory(start, end - start,
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start);
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break;
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case 1:
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/* ROM (XXX: not quite correct) */
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cpu_register_physical_memory(start, end - start,
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start | IO_MEM_ROM);
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break;
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case 2:
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case 0:
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/* XXX: should distinguish read/write cases */
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for(addr = start; addr < end; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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break;
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}
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}
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static void i440fx_update_memory_mappings(PCIDevice *d)
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{
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int i, r;
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uint32_t smram, addr;
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update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
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for(i = 0; i < 12; i++) {
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r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
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update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
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}
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smram = d->config[0x72];
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if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
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cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
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} else {
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for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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}
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}
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void i440fx_set_smm(PCIDevice *d, int val)
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{
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val = (val != 0);
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if (smm_enabled != val) {
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smm_enabled = val;
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i440fx_update_memory_mappings(d);
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}
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}
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/* XXX: suppress when better memory API. We make the assumption that
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no device (in particular the VGA) changes the memory mappings in
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the 0xa0000-0x100000 range */
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void i440fx_init_memory_mappings(PCIDevice *d)
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{
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int i;
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for(i = 0; i < 96; i++) {
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isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
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}
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}
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static void i440fx_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(d, address, val, len);
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if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
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i440fx_update_memory_mappings(d);
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}
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static void i440fx_save(QEMUFile* f, void *opaque)
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{
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PCIDevice *d = opaque;
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int i;
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pci_device_save(d, f);
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qemu_put_8s(f, &smm_enabled);
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for (i = 0; i < 4; i++)
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qemu_put_be32(f, pci_irq_levels[i]);
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}
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static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
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{
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PCIDevice *d = opaque;
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int ret, i;
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if (version_id > 2)
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return -EINVAL;
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ret = pci_device_load(d, f);
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if (ret < 0)
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return ret;
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i440fx_update_memory_mappings(d);
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qemu_get_8s(f, &smm_enabled);
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if (version_id >= 2)
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for (i = 0; i < 4; i++)
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pci_irq_levels[i] = qemu_get_be32(f);
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return 0;
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}
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PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
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{
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PCIBus *b;
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PCIDevice *d;
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I440FXState *s;
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s = qemu_mallocz(sizeof(I440FXState));
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b = pci_register_bus(NULL, "pci",
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piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
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s->bus = b;
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register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
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register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
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register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
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register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
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register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
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register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
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register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
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register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
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d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
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NULL, i440fx_write_config);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
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d->config[0x08] = 0x02; // revision
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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d->config[0x72] = 0x02; /* SMRAM */
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register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
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*pi440fx_state = d;
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return b;
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}
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/* PIIX3 PCI to ISA bridge */
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static PCIDevice *piix3_dev;
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PCIDevice *piix4_dev;
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static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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pci_irq_levels[irq_num] = level;
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = piix3_dev->config[0x60 + irq_num];
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if (pic_irq < 16) {
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/* The pic level is the logical OR of all the PCI irqs mapped
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to it */
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pic_level = 0;
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for (i = 0; i < 4; i++) {
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if (pic_irq == piix3_dev->config[0x60 + i])
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pic_level |= pci_irq_levels[i];
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}
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qemu_set_irq(pic[pic_irq], pic_level);
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}
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}
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static void piix3_reset(void *opaque)
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{
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x80;
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pci_conf[0x61] = 0x80;
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pci_conf[0x62] = 0x80;
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pci_conf[0x63] = 0x80;
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
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}
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static void piix4_reset(void *opaque)
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{
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config;
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pci_conf[0x04] = 0x07; // master, memory and I/O
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pci_conf[0x05] = 0x00;
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pci_conf[0x06] = 0x00;
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pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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pci_conf[0x4c] = 0x4d;
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pci_conf[0x4e] = 0x03;
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pci_conf[0x4f] = 0x00;
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pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
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pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
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pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
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pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
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pci_conf[0x69] = 0x02;
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pci_conf[0x70] = 0x80;
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pci_conf[0x76] = 0x0c;
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pci_conf[0x77] = 0x0c;
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pci_conf[0x78] = 0x02;
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pci_conf[0x79] = 0x00;
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pci_conf[0x80] = 0x00;
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pci_conf[0x82] = 0x00;
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pci_conf[0xa0] = 0x08;
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pci_conf[0xa2] = 0x00;
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pci_conf[0xa3] = 0x00;
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pci_conf[0xa4] = 0x00;
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pci_conf[0xa5] = 0x00;
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pci_conf[0xa6] = 0x00;
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pci_conf[0xa7] = 0x00;
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pci_conf[0xa8] = 0x0f;
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pci_conf[0xaa] = 0x00;
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pci_conf[0xab] = 0x00;
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pci_conf[0xac] = 0x00;
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pci_conf[0xae] = 0x00;
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memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
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}
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static void piix_save(QEMUFile* f, void *opaque)
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{
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PCIDevice *d = opaque;
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pci_device_save(d, f);
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}
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static int piix_load(QEMUFile* f, void *opaque, int version_id)
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{
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PCIDevice *d = opaque;
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if (version_id != 2)
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return -EINVAL;
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return pci_device_load(d, f);
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}
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int piix3_init(PCIBus *bus, int devfn)
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{
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PCIDevice *d;
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uint8_t *pci_conf;
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d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
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devfn, NULL, NULL);
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register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
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piix3_dev = d;
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pci_conf = d->config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
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pci_conf[PCI_HEADER_TYPE] =
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PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
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piix3_reset(d);
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qemu_register_reset(piix3_reset, 0, d);
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return d->devfn;
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}
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int piix4_init(PCIBus *bus, int devfn)
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{
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PCIDevice *d;
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uint8_t *pci_conf;
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d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
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devfn, NULL, NULL);
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register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
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piix4_dev = d;
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pci_conf = d->config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
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pci_conf[PCI_HEADER_TYPE] =
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PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
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piix4_reset(d);
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qemu_register_reset(piix4_reset, 0, d);
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return d->devfn;
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}
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