1adf24708b
A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets have a common basic set of registers and This model will provide the registers functionality for common registers of nest chiplet (Pervasive Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets) This commit implement the read/write functions of chiplet control registers. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
33 lines
959 B
C
33 lines
959 B
C
/*
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* QEMU PowerPC nest pervasive common chiplet model
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*
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* Copyright (c) 2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PPC_PNV_NEST_CHIPLET_PERVASIVE_H
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#define PPC_PNV_NEST_CHIPLET_PERVASIVE_H
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#define TYPE_PNV_NEST_CHIPLET_PERVASIVE "pnv-nest-chiplet-pervasive"
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#define PNV_NEST_CHIPLET_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_CHIPLET_PERVASIVE)
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typedef struct PnvPervasiveCtrlRegs {
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#define PNV_CPLT_CTRL_SIZE 6
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uint64_t cplt_ctrl[PNV_CPLT_CTRL_SIZE];
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uint64_t cplt_cfg0;
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uint64_t cplt_cfg1;
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uint64_t cplt_stat0;
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uint64_t cplt_mask0;
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uint64_t ctrl_protect_mode;
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uint64_t ctrl_atomic_lock;
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} PnvPervasiveCtrlRegs;
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typedef struct PnvNestChipletPervasive {
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DeviceState parent;
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MemoryRegion xscom_ctrl_regs_mr;
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PnvPervasiveCtrlRegs control_regs;
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} PnvNestChipletPervasive;
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#endif /*PPC_PNV_NEST_CHIPLET_PERVASIVE_H */
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