492 lines
16 KiB
C
492 lines
16 KiB
C
/*
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* vm86 linux syscall support
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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//#define DEBUG_VM86
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#ifdef DEBUG_VM86
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# define LOG_VM86(...) qemu_log(__VA_ARGS__);
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#else
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# define LOG_VM86(...) do { } while (0)
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#endif
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#define set_flags(X,new,mask) \
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((X) = ((X) & ~(mask)) | ((new) & (mask)))
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#define SAFE_MASK (0xDD5)
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#define RETURN_MASK (0xDFF)
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static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
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{
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return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1;
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}
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static inline void vm_putw(CPUX86State *env, uint32_t segptr,
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unsigned int reg16, unsigned int val)
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{
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cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
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}
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static inline void vm_putl(CPUX86State *env, uint32_t segptr,
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unsigned int reg16, unsigned int val)
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{
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cpu_stl_data(env, segptr + (reg16 & 0xffff), val);
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}
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static inline unsigned int vm_getb(CPUX86State *env,
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uint32_t segptr, unsigned int reg16)
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{
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return cpu_ldub_data(env, segptr + (reg16 & 0xffff));
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}
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static inline unsigned int vm_getw(CPUX86State *env,
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uint32_t segptr, unsigned int reg16)
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{
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return cpu_lduw_data(env, segptr + (reg16 & 0xffff));
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}
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static inline unsigned int vm_getl(CPUX86State *env,
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uint32_t segptr, unsigned int reg16)
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{
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return cpu_ldl_data(env, segptr + (reg16 & 0xffff));
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}
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void save_v86_state(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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struct target_vm86plus_struct * target_v86;
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if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
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/* FIXME - should return an error */
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return;
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/* put the VM86 registers in the userspace register structure */
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target_v86->regs.eax = tswap32(env->regs[R_EAX]);
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target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
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target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
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target_v86->regs.edx = tswap32(env->regs[R_EDX]);
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target_v86->regs.esi = tswap32(env->regs[R_ESI]);
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target_v86->regs.edi = tswap32(env->regs[R_EDI]);
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target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
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target_v86->regs.esp = tswap32(env->regs[R_ESP]);
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target_v86->regs.eip = tswap32(env->eip);
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target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
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target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
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target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
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target_v86->regs.es = tswap16(env->segs[R_ES].selector);
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target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
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target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
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set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
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target_v86->regs.eflags = tswap32(env->eflags);
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unlock_user_struct(target_v86, ts->target_v86, 1);
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LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
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env->eflags, env->segs[R_CS].selector, env->eip);
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/* restore 32 bit registers */
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env->regs[R_EAX] = ts->vm86_saved_regs.eax;
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env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
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env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
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env->regs[R_EDX] = ts->vm86_saved_regs.edx;
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env->regs[R_ESI] = ts->vm86_saved_regs.esi;
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env->regs[R_EDI] = ts->vm86_saved_regs.edi;
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env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
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env->regs[R_ESP] = ts->vm86_saved_regs.esp;
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env->eflags = ts->vm86_saved_regs.eflags;
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env->eip = ts->vm86_saved_regs.eip;
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cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
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cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
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cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
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cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
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cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
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cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
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}
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/* return from vm86 mode to 32 bit. The vm86() syscall will return
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'retval' */
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static inline void return_to_32bit(CPUX86State *env, int retval)
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{
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LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
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save_v86_state(env);
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env->regs[R_EAX] = retval;
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}
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static inline int set_IF(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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ts->v86flags |= VIF_MASK;
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if (ts->v86flags & VIP_MASK) {
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return_to_32bit(env, TARGET_VM86_STI);
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return 1;
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}
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return 0;
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}
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static inline void clear_IF(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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ts->v86flags &= ~VIF_MASK;
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}
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static inline void clear_TF(CPUX86State *env)
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{
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env->eflags &= ~TF_MASK;
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}
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static inline void clear_AC(CPUX86State *env)
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{
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env->eflags &= ~AC_MASK;
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}
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static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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set_flags(ts->v86flags, eflags, ts->v86mask);
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set_flags(env->eflags, eflags, SAFE_MASK);
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if (eflags & IF_MASK)
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return set_IF(env);
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else
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clear_IF(env);
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return 0;
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}
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static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
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set_flags(env->eflags, flags, SAFE_MASK);
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if (flags & IF_MASK)
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return set_IF(env);
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else
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clear_IF(env);
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return 0;
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}
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static inline unsigned int get_vflags(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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unsigned int flags;
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flags = env->eflags & RETURN_MASK;
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if (ts->v86flags & VIF_MASK)
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flags |= IF_MASK;
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flags |= IOPL_MASK;
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return flags | (ts->v86flags & ts->v86mask);
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}
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#define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)
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/* handle VM86 interrupt (NOTE: the CPU core currently does not
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support TSS interrupt revectoring, so this code is always executed) */
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static void do_int(CPUX86State *env, int intno)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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uint32_t int_addr, segoffs, ssp;
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unsigned int sp;
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if (env->segs[R_CS].selector == TARGET_BIOSSEG)
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goto cannot_handle;
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if (is_revectored(intno, &ts->vm86plus.int_revectored))
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goto cannot_handle;
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if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
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&ts->vm86plus.int21_revectored))
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goto cannot_handle;
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int_addr = (intno << 2);
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segoffs = cpu_ldl_data(env, int_addr);
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if ((segoffs >> 16) == TARGET_BIOSSEG)
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goto cannot_handle;
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LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
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intno, segoffs >> 16, segoffs & 0xffff);
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/* save old state */
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ssp = env->segs[R_SS].selector << 4;
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sp = env->regs[R_ESP] & 0xffff;
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vm_putw(env, ssp, sp - 2, get_vflags(env));
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vm_putw(env, ssp, sp - 4, env->segs[R_CS].selector);
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vm_putw(env, ssp, sp - 6, env->eip);
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ADD16(env->regs[R_ESP], -6);
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/* goto interrupt handler */
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env->eip = segoffs & 0xffff;
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cpu_x86_load_seg(env, R_CS, segoffs >> 16);
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clear_TF(env);
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clear_IF(env);
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clear_AC(env);
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return;
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cannot_handle:
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LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
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return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
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}
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void handle_vm86_trap(CPUX86State *env, int trapno)
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{
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if (trapno == 1 || trapno == 3) {
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return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
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} else {
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do_int(env, trapno);
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}
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}
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#define CHECK_IF_IN_TRAP() \
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if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
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(ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \
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newflags |= TF_MASK
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#define VM86_FAULT_RETURN \
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if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
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(ts->v86flags & (IF_MASK | VIF_MASK))) \
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return_to_32bit(env, TARGET_VM86_PICRETURN); \
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return
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void handle_vm86_fault(CPUX86State *env)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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uint32_t csp, ssp;
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unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
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int data32, pref_done;
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csp = env->segs[R_CS].selector << 4;
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ip = env->eip & 0xffff;
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ssp = env->segs[R_SS].selector << 4;
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sp = env->regs[R_ESP] & 0xffff;
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LOG_VM86("VM86 exception %04x:%08x\n",
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env->segs[R_CS].selector, env->eip);
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data32 = 0;
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pref_done = 0;
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do {
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opcode = vm_getb(env, csp, ip);
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ADD16(ip, 1);
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switch (opcode) {
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case 0x66: /* 32-bit data */ data32=1; break;
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case 0x67: /* 32-bit address */ break;
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case 0x2e: /* CS */ break;
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case 0x3e: /* DS */ break;
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case 0x26: /* ES */ break;
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case 0x36: /* SS */ break;
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case 0x65: /* GS */ break;
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case 0x64: /* FS */ break;
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case 0xf2: /* repnz */ break;
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case 0xf3: /* rep */ break;
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default: pref_done = 1;
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}
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} while (!pref_done);
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/* VM86 mode */
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switch(opcode) {
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case 0x9c: /* pushf */
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if (data32) {
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vm_putl(env, ssp, sp - 4, get_vflags(env));
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ADD16(env->regs[R_ESP], -4);
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} else {
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vm_putw(env, ssp, sp - 2, get_vflags(env));
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ADD16(env->regs[R_ESP], -2);
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}
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env->eip = ip;
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VM86_FAULT_RETURN;
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case 0x9d: /* popf */
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if (data32) {
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newflags = vm_getl(env, ssp, sp);
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ADD16(env->regs[R_ESP], 4);
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} else {
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newflags = vm_getw(env, ssp, sp);
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ADD16(env->regs[R_ESP], 2);
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}
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env->eip = ip;
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CHECK_IF_IN_TRAP();
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if (data32) {
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if (set_vflags_long(newflags, env))
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return;
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} else {
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if (set_vflags_short(newflags, env))
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return;
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}
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VM86_FAULT_RETURN;
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case 0xcd: /* int */
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intno = vm_getb(env, csp, ip);
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ADD16(ip, 1);
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env->eip = ip;
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if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
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if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >>
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(intno &7)) & 1) {
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return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
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return;
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}
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}
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do_int(env, intno);
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break;
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case 0xcf: /* iret */
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if (data32) {
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newip = vm_getl(env, ssp, sp) & 0xffff;
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newcs = vm_getl(env, ssp, sp + 4) & 0xffff;
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newflags = vm_getl(env, ssp, sp + 8);
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ADD16(env->regs[R_ESP], 12);
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} else {
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newip = vm_getw(env, ssp, sp);
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newcs = vm_getw(env, ssp, sp + 2);
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newflags = vm_getw(env, ssp, sp + 4);
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ADD16(env->regs[R_ESP], 6);
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}
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env->eip = newip;
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cpu_x86_load_seg(env, R_CS, newcs);
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CHECK_IF_IN_TRAP();
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if (data32) {
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if (set_vflags_long(newflags, env))
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return;
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} else {
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if (set_vflags_short(newflags, env))
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return;
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}
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VM86_FAULT_RETURN;
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case 0xfa: /* cli */
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env->eip = ip;
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clear_IF(env);
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VM86_FAULT_RETURN;
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case 0xfb: /* sti */
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env->eip = ip;
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if (set_IF(env))
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return;
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VM86_FAULT_RETURN;
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default:
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/* real VM86 GPF exception */
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return_to_32bit(env, TARGET_VM86_UNKNOWN);
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break;
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}
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}
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int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
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{
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CPUState *cs = env_cpu(env);
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TaskState *ts = cs->opaque;
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struct target_vm86plus_struct * target_v86;
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int ret;
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switch (subfunction) {
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case TARGET_VM86_REQUEST_IRQ:
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case TARGET_VM86_FREE_IRQ:
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case TARGET_VM86_GET_IRQ_BITS:
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case TARGET_VM86_GET_AND_RESET_IRQ:
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qemu_log_mask(LOG_UNIMP, "qemu: unsupported vm86 subfunction (%ld)\n",
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subfunction);
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ret = -TARGET_EINVAL;
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goto out;
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case TARGET_VM86_PLUS_INSTALL_CHECK:
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/* NOTE: on old vm86 stuff this will return the error
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from verify_area(), because the subfunction is
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interpreted as (invalid) address to vm86_struct.
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So the installation check works.
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*/
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ret = 0;
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goto out;
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}
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/* save current CPU regs */
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ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
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ts->vm86_saved_regs.ebx = env->regs[R_EBX];
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ts->vm86_saved_regs.ecx = env->regs[R_ECX];
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ts->vm86_saved_regs.edx = env->regs[R_EDX];
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ts->vm86_saved_regs.esi = env->regs[R_ESI];
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ts->vm86_saved_regs.edi = env->regs[R_EDI];
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ts->vm86_saved_regs.ebp = env->regs[R_EBP];
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ts->vm86_saved_regs.esp = env->regs[R_ESP];
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ts->vm86_saved_regs.eflags = env->eflags;
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ts->vm86_saved_regs.eip = env->eip;
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ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
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ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
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ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
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ts->vm86_saved_regs.es = env->segs[R_ES].selector;
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ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
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ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
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ts->target_v86 = vm86_addr;
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if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1))
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return -TARGET_EFAULT;
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/* build vm86 CPU state */
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ts->v86flags = tswap32(target_v86->regs.eflags);
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env->eflags = (env->eflags & ~SAFE_MASK) |
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(tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;
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ts->vm86plus.cpu_type = tswapal(target_v86->cpu_type);
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switch (ts->vm86plus.cpu_type) {
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case TARGET_CPU_286:
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ts->v86mask = 0;
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break;
|
|
case TARGET_CPU_386:
|
|
ts->v86mask = NT_MASK | IOPL_MASK;
|
|
break;
|
|
case TARGET_CPU_486:
|
|
ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK;
|
|
break;
|
|
default:
|
|
ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
|
|
break;
|
|
}
|
|
|
|
env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
|
|
env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
|
|
env->regs[R_EDX] = tswap32(target_v86->regs.edx);
|
|
env->regs[R_ESI] = tswap32(target_v86->regs.esi);
|
|
env->regs[R_EDI] = tswap32(target_v86->regs.edi);
|
|
env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
|
|
env->regs[R_ESP] = tswap32(target_v86->regs.esp);
|
|
env->eip = tswap32(target_v86->regs.eip);
|
|
cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
|
|
cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
|
|
cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
|
|
cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
|
|
cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
|
|
cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
|
|
ret = tswap32(target_v86->regs.eax); /* eax will be restored at
|
|
the end of the syscall */
|
|
memcpy(&ts->vm86plus.int_revectored,
|
|
&target_v86->int_revectored, 32);
|
|
memcpy(&ts->vm86plus.int21_revectored,
|
|
&target_v86->int21_revectored, 32);
|
|
ts->vm86plus.vm86plus.flags = tswapal(target_v86->vm86plus.flags);
|
|
memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab,
|
|
target_v86->vm86plus.vm86dbg_intxxtab, 32);
|
|
unlock_user_struct(target_v86, vm86_addr, 0);
|
|
|
|
LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
|
|
env->segs[R_CS].selector, env->eip);
|
|
/* now the virtual CPU is ready for vm86 execution ! */
|
|
out:
|
|
return ret;
|
|
}
|