Benjamin Herrenschmidt 97ed5ccdee tlb: Add "ifetch" argument to cpu_mmu_index() ... This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>		2015-09-11 08:15:28 -07:00
..
cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	cpu: Change cpu_exec_init() arg to cpu, not env	2015-07-09 15:20:40 +02:00
cpu.h	tlb: Add "ifetch" argument to cpu_mmu_index()	2015-09-11 08:15:28 -07:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	maint: remove unused include for signal.h	2015-09-11 10:21:38 +03:00
helper.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
Makefile.objs	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
op_helper.c	target-tricore: fix depositing bits from PCXI into ICR	2015-06-29 14:02:58 +02:00
translate.c	tlb: Add "ifetch" argument to cpu_mmu_index()	2015-09-11 08:15:28 -07:00
tricore-defs.h	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
tricore-opcodes.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00